Executive Summary
Semiconductors are the foundational technology enabling virtually every aspect of contemporary economic activity, from artificial intelligence and cloud computing to medical devices and automotive systems. The competitive dynamics of semiconductor manufacturing directly determine the accessibility and affordability of computing power across all industries, shaping innovation, productivity, and the broader welfare gains that flow from digital technologies.
Despite its central importance, the industry’s fundamental economics are not well-understood, risking policy actions that could stifle the innovation engine that has powered the digital revolution. This paper demystifies those fundamental economic forces and clarifies the nature of competition in the semiconductor manufacturing industry.
Moore’s Law and Rock’s Law Create Unique Competitive Pressures
Two unique, interconnected technological imperatives define semiconductor manufacturing competition.
- Moore’s Law began as a rule of thumb about transistor counts doubling at a steady cadence. Today its practical meaning is broader: customers expect predictable gains in overall performance per watt and per dollar, and delivered on schedule. That pushes the industry through a relentless metronome of “beats,” where each node (manufacturing generation) must arrive on time with real, measurable gains. Falling behind by a single beat can cost customers for years.
- Rock’s Law is the darker side of Moore’s Law. It holds that, as chips get denser, the cost of making them rises exponentially. Advanced fabs now cost $10–20 billion, and a single high-NA EUV scanner (the heart of leading-edge lithography) runs north of $400 million. These are not scale or inflation artifacts; they’re the price of pushing matter toward the level of atomic precision demanded by Moore’s Law.
Together, these forces create recurring, high-stakes races unmatched by any other market in the world. In these races, firms must commit massive resources years in advance, under extreme uncertainty.
These technological forces produce a recurring “competition for the market” rather than “competition in the market”—a distinction that matters for understanding the market’s structure and dynamics. Unlike industries with relatively stable market structures, semiconductor manufacturing features periodic technological disruptions that can entirely reset competitive positions. Each new process node represents a fresh competition in which previous leaders may fall behind, and laggards may leapfrog ahead.
High Stakes and High Profits: Three Forces Shaping Competition
The pressures of Moore’s and Rock’s Laws and the sequential nature of innovation in semiconductor manufacturing force chipmakers into a recurring gamble: commit extraordinary sums to the next node—years before demand is certain and before yields are proven—or risk slipping behind. This dynamic creates the most high-stakes, high-risk competitive environment in modern manufacturing, in which massive upfront investments, technological uncertainty, market volatility, and supply-chain dependencies combine to create multiple layers of risk that even the most sophisticated firms struggle to manage. This environment is characterized by:
- Front-loaded capital risk: Leaders routinely invest tens of billions of dollars years before demand is certain. TSMC’s CapEx, for example, has run 30–50% of revenue since 2009 (peaking above 50% in 2021); including R&D, investment often exceeds 40–60% of revenue. These are existential bets, not routine expenditures. A missed bet doesn’t just mean a bad quarter; it results in stranded assets.
- Technology & execution risk: Each node is a multi-front physics problem involving (among other things) lithography, new transistor structures, novel materials, power delivery, metrology, and advanced packaging. A single miscalculated process decision can torpedo a firm’s reputation and ripple across years of products. Even the most successful firms experience bruising challenges securing sufficient yields deploying new technology on the way to securing reliable production volumes.
- Timing & demand risk: Firms must guess the right capacity, on the right node, for markets that may not exist yet. Miss the cycle and the firm is saddled with an expensive, idle plant; overshoot and it fuels a downturn. In this environment money alone cannot conjure the know-how or managerial coordination required to succeed.
These Forces Have Pushed the Industry Toward a Unique Structure of Specialization and Relational Contracting
The historical transformation from vertically integrated device manufacturers (IDMs) like Intel to the modern foundry model exemplified by TSMC represents an efficiency-enhancing response to Rock’s Law. As the cost and technological demands of manufacturing at the bleeding edge became unsustainable for non-specialized firms, the development of standardized design tools and collaboration routines lowered coordination costs. These enabled a separation of design and manufacturing which, in turn, facilitated valuable specialization and risk-sharing: Independent foundries aggregate demand across multiple customers, achieving economies of scale difficult for IDMs to reach, while also keeping their expensive fabrication equipment fully utilized.
This specialization created concrete economic benefits. Independent foundries achieve higher equipment utilization by serving diverse customers with different demand cycles. They spread enormous R&D costs across multiple clients rather than bearing them alone. The fabless model allowed companies like Nvidia to focus entirely on GPU architecture without operating fabs, while Qualcomm could specialize in wireless chips, and Broadcom in networking semiconductors. Meanwhile, each could access the same cutting-edge manufacturing technology that previously only giants like Intel could afford.
These sophisticated relationships are governed by relational contracts—contractual relationships whose precise terms depend on cooperative adjustments by the parties over time—and complex governance structures that solve extraordinary coordination challenges more efficiently than vertical integration or spot-market transactions. When capital investments reach tens of billions of dollars per facility and must be committed years before demand is certain, both foundries and their customers make relationship-specific investments that create bilateral dependence. Rather than evidence of market failure, these arrangements are market-based solutions enabling the massive, risky investments required for continued innovation.
Competition Occurs Through the Development of Dynamic Capabilities and the Relentless March of Creative Destruction
In this contest, what sustains success is not static market position but dynamic capabilities: a firm’s organizational capacity to sense opportunities, seize them through massive investments, and transform operations to deliver on technological transitions. Strong dynamic capabilities are much more significant than existing market shares as predictors of competitive outcomes. TSMC’s exceptional customer sensing and early EUV investments allowed it to surge ahead when Intel stumbled at 10nm, starkly demonstrating that leadership in advanced semiconductors depends on who redefines the technological frontier and executes the massive investments required. But this is not unique to TSMC. Samsung’s rapid technology absorption and Intel’s attempted pivot to foundry services all demonstrate how organizational capabilities, not market structure, determine competitive outcomes. Each technology generation triggers a new cycle of sensing, seizing, and transforming, with market positions reconstructed at each discontinuity.
Traditional static measures of market power—concentration ratios, market shares, profit margins—systematically mischaracterize this competitive environment. They confuse the temporary rewards of successful innovation with durable market power and mistake the efficient consolidation of an industry with scale economies for anticompetitive concentration. Two economic lenses help decode profits and market shares in chips:
- Returns to scarcity or “Ricardian rents” stem from owning unique productive assets or capabilities that others cannot easily replicate. They do not necessarily entail reduced output; the firm is simply so much more efficient or uniquely positioned that others cannot replicate it. ASML’s high margins, for example, reflect a Ricardian rent based on its unique technology, not a manipulative output restriction.
- Returns to entrepreneurship or “Schumpeterian rents” are earned by innovators due to a temporary lead before imitators catch up. These arise because technological imitation is not instantaneous; a firm that first commercializes a breakthrough chip or process can enjoy outsized profits for a period, even as it actively produces at full capacity. Such innovation returns are transient, however, and readily dissipated by the leader’s massive capital expenditures spent in the expectation that a challenger is always right around the corner.
Both types of returns are beneficial from an innovation-policy perspective as they incentivize enormous investments in R&D and capital. By the same token, static concentration and profitability metrics may be misleading as concentration may reflect efficient specialization rather than lessened competition, high returns may represent innovation rents rather than monopoly profits, and complex contractual relationships may solve coordination problems rather than exclude rivals.
I. Moore’s Law and Rock’s Law: Twin Drivers of Exponential Change
The semiconductor[1] manufacturing industry represents one of the most dynamic and consequential competitive arenas in the modern economy. Unlike traditional manufacturing sectors, where competitive advantage might stem from operational efficiency, brand recognition, or distribution networks, semiconductor competition is fundamentally shaped by two interconnected technological imperatives that create a unique and unforgiving competitive environment. Understanding these imperatives—and the market dynamics they generate—is essential for policymakers, researchers, investors, and industry participants seeking to assess competition in the industry.
Semiconductors are the foundational technology enabling virtually every aspect of modern economic activity, from artificial intelligence and cloud computing to medical devices and automotive systems. The stakes could not be higher. The competitive dynamics of semiconductor manufacturing directly determine the accessibility and affordability of computing power across all industries, shaping innovation, productivity, and the broader welfare gains that flow from digital technologies. Yet despite its central importance, recent policy discussions have often misunderstood the industry’s fundamental economics, risking interventions that could stifle the innovation engine that has powered the digital revolution.
While the broader semiconductor industry includes a wide range of international players, including both designers and producers of both logic and memory chips, this paper focuses on the competition landscape of the logic chip manufacturing segment,[2] where firms such as Samsung, Taiwan Semiconductor Manufacturing Company (“TSMC”), Intel, GlobalFoundries Inc., United Microelectronics Corporation (“UMC”), and Semiconductor Manufacturing International Corp. (“SMIC”) are the main participants.
A. Fundamental Investment Pressures
Two deceptively simple observations explain almost everything about how chip manufacturing markets behave and why competition in them (or, for them) takes such a distinctive form. The first is Moore’s Law, the famous prediction that transistor counts per chip (and thus potential performance per chip) roughly double on a predictable cadence.[3] This relentless technological progress has driven decades of compounding improvements and falling cost per unit of compute, creating the foundation for our digital economy. The regularity of this advancement means the industry moves in a relentless series of technology competition cycles, or “beats,” with each generation promising more performance at lower cost per transistor. The result is a set of customer and industry expectations that fuels an intense and relentless rivalry in which firms must constantly innovate simply to maintain their relative position, much like the Red Queen in Lewis Carroll’s tale, who must run constantly just to stay in place.[4]
Today, keeping pace with Moore’s Law is less about the number of transistors in a single integrated circuit per se, and more about overall performance—which increasingly depends not only on the development of ever-smaller transistors, but also on new materials technology, energy efficiency, novel transistor structures, design-technology optimization,[5] and advanced packaging.[6]
Figure 1: Potential roadmap extension for chip nodes
Source: imec’s chip scaling roadmap[7]
Figure 2: Advances in semiconductor technology [top line]—including new materials, advances in lithography, new types of transistors, and advanced packaging
Source: Mark Liu & H.-S. Philip Wong (2024)[8]
But Moore’s Law alone cannot explain the fierce competitive dynamics that define semiconductor manufacturing. There’s a second, less-celebrated rule that sets the stakes: Rock’s Law (sometimes described as “Moore’s Second Law”).[9] As chips get denser, the cost of manufacturing capacity rises exponentially.[10] In practical terms, each new generation of fabs[11] and equipment is vastly more expensive than the last. In the late 1960s, a cutting-edge semiconductor fab cost on the order of a few million dollars to build; by the early 2000s, it had escalated to the low billions.[12] Today, a single advanced, leading-edge fab in the U.S. (for nodes under 4nm) can cost $10–20 billion or more.[13] This exponential cost escalation is not merely a matter of inflation or scale. It reflects the fundamental physics of pushing manufacturing precision to near-atomic limits.[14]
Consider the sheer magnitude: Intel is currently building two new fabs in Arizona, originally projected to cost about $20 billion each, while Samsung’s upcoming fabs in Taylor, Texas, are estimated to cost around $37 billion. TSMC’s original investment for three fabs in Phoenix, Arizona, totaled $65 billion.[15] A high-NA EUV scanner—the ASML device at the heart of bleeding-edge semiconductor manufacturing, described as “the most complicated machine humans have built”[16]—alone costs over $400 million.[17]
These massive capital expenditures must be regularly and continually reinvested to manufacture each new node. Leading firms invest tens of billions annually on new facilities and equipment. TSMC, for example, budgeted roughly $36 billion in capital expenditure in 2022 to expand and upgrade its fabs, $30 billion in 2023, and another $29 billion in 2024 (See Table 1, below).[18] Intel and Samsung have similarly outsized spending expectations, with Intel recently announcing a multiyear, $100 billion expected investment plan,[19] although the future of that investment remains unknown given the U.S. government recently acquired a stake in the company.[20]
In addition, significant research and development (R&D) investment is also required to keep up with Moore’s Law. If we zoom out beyond just manufacturing to where we have better data, the semiconductor industry as a whole is one of the most R&D intensive industries in the world, typically ranking third or fourth after the pharmaceutical, biotech, and/or software industries. In 2024, overall U.S. semiconductor industry investment in R&D totaled $62.7 billion, representing 18% of U.S. semiconductor firms’ revenue.[21] For Intel (which, it is worth noting, invests in both design and manufacturing), U.S. R&D expenses in 2024 totaled $16.5 billion, or a massive 31% of the company’s revenue, while TSMC spent $6.4 billion on R&D in 2024.[22]
Figure 3: U.S. Semiconductor R&D Expenditure Percent of Sales by Industry
Source: SIA Factbook[23]
These company-specific investments reflect broader industry patterns. Across the U.S. semiconductor industry as a whole, combined capital expenditures and R&D spending have grown dramatically over the past two decades. Industry-wide investment increased from approximately $28 billion in 2001 to $119.5 billion in 2024—representing a compound annual growth rate of 6.4 percent, but higher since 2020.[24] More significantly, this investment intensity has remained remarkably stable as a percentage of sales despite market cyclicality, consistently hovering around 30% of revenue throughout this period.[25]
Figure 4: U.S. Semiconductor R&D and Capital Expenditures
Source: SIA Factbook[26]
The scale of per-employee investment further illustrates the capital-intensive nature of the industry. In 2024, U.S. semiconductor firms invested an average of $235,007 per employee in combined R&D and capital expenditures—up from approximately $100,000 per employee in 2001.
The semiconductor industry’s R&D intensity stands out even among high-technology sectors. U.S. semiconductor firms consistently spend over 15% of sales on R&D—a rate exceeded only by the pharmaceutical and biotechnology industry among major U.S. industries. In 2024, semiconductor R&D spending reached 18% of revenue, compared to approximately 15.6% for software and computer services, 11.4% for semiconductor manufacturing equipment, and just 5.5% for consumer electronics.[27]
Figure 5: U.S. Semiconductor Capital and R&D Expenditures as a Percent of Sales
Source: SIA Factbook[28]
This commitment to R&D is not merely a U.S. phenomenon but reflects a strategic positioning: U.S. semiconductor firms spend more on R&D as a percentage of sales (17.7%) than their counterparts in any other country, including Korea (11.8%), Taiwan (11.5%), Europe (10.8%), China (9.2%), and Japan (5.7%).[29] This R&D leadership has been sustained for over two decades, enabling U.S. firms to maintain their technological edge and nearly 50% global market share despite intense international competition.
This relentless investment race is itself a fundamental form of competition. Companies that falter in their investment commitments can fall behind technologically, losing their ability to serve customers who demand the latest process nodes. Table 1 illustrates TSMC’s—a leading semiconductor manufacturer—investment intensity over time, demonstrating remarkably consistent capital expenditures of about 30–50% of revenue. It also reflects how the pattern of CapEx and R&D spending for the broader semiconductor industry is reflected in the semiconductor manufacturing niche, as well.
Table 1: TSMC Historical Annual Investment Intensity (2009–2024)
Sources: TSMC 4Q management reports, 2009-2023; Macrotrends revenue and R&D series[30]
This data reveals the extraordinary financial commitment required to remain competitive. The semiconductor manufacturing industry demands technical expertise, management acumen, and the financial wherewithal to sustain investments that would represent the entire market capitalization of most companies in other industries.[31]
B. The Implications of Moore’s and Rock’s Laws
Taken together, Moore’s Law and Rock’s Law create a simple but unforgiving competitive logic: the technological clock speeds up while the financial ante keeps rising. The cadence of Moore’s Law forces firms to be ready with demonstrably better technology on a tight timeline, while Rock’s Law means getting ready requires significant, front-loaded investment that must be committed years before demand is certain. This creates a recurring, high-stakes bet where companies must commit extraordinary sums to develop the next technology node before knowing whether customers will materialize or whether their technical approach will succeed.
For decades, the semiconductor manufacturing industry managed these costs and risks under a vertically integrated business model. So-called integrated device manufacturers (IDMs) like Intel, IBM, and Texas Instruments handled the entire microchip creation process, from design and R&D to manufacturing and deployment. This model made economic sense when fabs cost millions rather than billions, when individual companies could achieve efficient scale in manufacturing, and when the tight coupling of design and manufacturing knowledge created competitive advantages.[32] But by the 1980s, the economics were beginning to shift. Rock’s Law was making it increasingly difficult for any single company to bear the full cost of staying at the technological frontier. At the same time, the semiconductor market was fragmenting from standardized products into thousands of specialized applications, each with different volume requirements.
Rock’s Law generated a fundamental reorganization of the industry driven by two complementary forces. First, as noted, the exploding fixed costs and execution risks of each new node made duplicated, in-house fabs economically inefficient and made underutilization of built capacity ruinously expensive. Second, and equally important, necessity and invention reduced the costs of vertically separated production and design. For example, standardization of design tools, manufacturing interfaces, and collaboration workflows dramatically reduced the transaction costs of coordinating across firm boundaries. Electronic design automation (EDA) tools became standardized around common languages and methodologies. Foundries developed comprehensive process design kits (PDKs) that allowed external designers to tailor their designs to a foundry’s specific manufacturing processes without mastering proprietary details. Digital collaboration platforms enabled real-time coordination between designers and manufacturers separated by oceans and organizational boundaries.
These changes fundamentally flipped the underlying economics of semiconductor manufacturing and ushered in a new golden age. An independent foundry could aggregate demand from many customers, keeping billion-dollar tools fully loaded and climbing learning curves faster than any integrated manufacturer. For chip designers, the massive, fixed cost of fab ownership converted into a variable cost paid per wafer, enabling thousands of specialized design companies to emerge where only dozens had existed before.
One predictable result of this shift was an increase in market concentration. But rather than a signal of less competition, this concentration was driven by economic efficiency—cheaper, faster technology development in a world where Moore’s cadence and Rock’s costs punish duplication and reward scale.
The competitive implications of these two laws should shape how we think about market power and competitive dynamics in this industry. When the cost of entry to the next node represents a tens-of-billion-dollar, multi-year commitment, firms must take extraordinary risks and must earn commensurate rewards to justify continued investment. At any given point, therefore, a static snapshot of market shares or profits could be misleading, suggesting a high degree of market power, but actually representing only a temporary return on investment.
Crucially, this is not a one-time race. Because each generation of chips resets the performance bar, the “losers” have an opportunity to strike back, and the “winners” face a renewed threat that is largely independent of previous success. Winners, in this sense, do not enjoy “monopoly rents” but rather temporary “innovation returns”[33]—resources that must be substantially dedicated to funding the next round in order to maintain market share. High returns or market share at any given moment thus likely reflect proportionate returns to superior execution in the most recent technology race rather than durable market power, and any gains may be transitory, as competition for the next beat could see a reversal of fortune.[34] Indeed, competitive success in semiconductor manufacturing does not require constant technological leadership: UMC has maintained profitable businesses for years by focusing on mature nodes, including by partnering with Intel,[35] but now “may be preparing an unexpected return to the cutting-edge arena it once abandoned.”[36] Indeed, independent estimates suggest that TSMC’s most profitable offering in 2024 was its 7nm node, not the more advanced 5nm or 3nm nodes.[37]
This competitive dynamic requires a fundamental reassessment of how competition policy should operate. As discussed below, semiconductor manufacturing does not resemble a conventional “competition in the market” model. Instead, it evolves through repeated cycles of “competition for the market,” where firms undertake costly, high-risk technological races that reshape the competitive standings with each new process generation. In this context, traditional structuralist critiques—focused on static indicators such as concentration levels, market shares, or profit margins—rely on an incomplete analytical lens and miss the core economic reality. The industry’s business structures, partnerships, and contracting practices generally reflect adaptive mechanisms to manage extreme coordination, capital, and technological risks, not exclusionary tactics. These governance arrangements are what make sustained innovation and multi-billion-dollar investments possible.
Misinterpreting these features as evidence of entrenched market power risks prompting misguided interventions that would slow innovation, undermine entry, and ultimately constrict access to high-performance computing. Given the central role semiconductors play in modern technological progress, competition policy cannot afford to misread the competitive dynamics at play or adopt measures that inadvertently stifle the innovation it seeks to protect.
* * *
In the following sections, we unpack these dynamics in detail. Section II examines the three defining features of semiconductor manufacturing markets that make competition uniquely challenging: the industry’s extreme capital intensity and dependence on massive up-front investments, the extraordinary (and constant) technological and execution hurdles involved, and the high degree of uncertainty surrounding timing and demand. Section III explores the industrial-organization economics of semiconductor specialization, describing how semiconductor manufacturing evolved from a vertically integrated business model to the current fabless-foundry paradigm. Section IV explores how competition occurs through dynamic “races for the market” at each new technology node, where firms compete for temporary leadership positions that must be continuously re-earned through innovation and investment. Finally, Section V concludes with some preliminary policy implications, arguing that misguided interventions based on a naïve reliance on traditional competition metrics could undermine the very mechanisms that have driven the industry’s remarkable pace of innovation.
II. The Persistent Challenge: Investment Under Extreme Uncertainty
Moore’s cadence sets the clock; Rock’s costs raise the ante. Together they force chip manufacturers into a recurring gamble: commit extraordinary sums to the next node—years before demand is certain and before yields are proven—or risk slipping a full cycle behind. This dynamic creates what is perhaps the most high-stakes, high-risk competitive environment in modern manufacturing, where the combination of massive upfront investments, technological uncertainty, market volatility, and supply chain dependencies creates multiple layers of risk that even the most sophisticated firms struggle to manage.
A. Capital Intensity and Front-Loaded Investment Risk
The scale of capital requirements in semiconductor manufacturing represents the first and most obvious source of risk. To build next-generation capacity, foundries spend tens of billions of dollars in anticipation of future demand. In 2021, for example, at the height of COVID-induced chip shortages, TSMC famously announced a $100 billion, three-year CapEx plan to expand capacity and develop new nodes.[38] Intel and Micron subsequently each announced their own $100 billion U.S. CapEx investments.[39] Samsung likewise has been investing heavily, with, among others, a new $17 billion fab in Texas.[40]
As shown above, TSMC’s historical capital expenditures have consistently amounted to 30-50% of revenue, reaching as high as 52.5% in 2021. Including R&D—a necessary adjunct to CapEx spending in an industry marked by inexorable technological advance—the company’s 2021 investment represented over 60% of revenue.[41] These investments represent existential bets rather than routine expenditures. If the demand for a specific capacity or node doesn’t materialize (or if a technology bet goes wrong), the foundry can be left with huge sunk costs (and mounting debt). A recent significant order for Samsung chips by Tesla, for instance, “is poised to make this entire [Texas] fab viable, which is critical not only for the 2nm process, but the processes to follow.”[42] But that outcome was uncertain beforehand: just weeks prior, Samsung was poised to delay its fab investment due to a lack of customers.[43]
The front-loaded nature of these investments amplifies the risk. Unlike other industries where capacity can be added incrementally in response to proven demand, semiconductor fabs must be built and equipped years before the technology they will produce is commercially viable. A decision to invest in 2nm capacity today requires semiconductor manufacturers to make investments based on uncertain projections of market demand, technological feasibility, and competitive positioning three to four years in the future—an eternity in the technology sector. As explained later, semiconductor manufacturers have developed ways to manage this risk, but they cannot eliminate it.[44]
B. Technological and Execution Risk
As crucial as it is, capital alone is insufficient to guarantee success in this industry. Indeed, as Rock’s Law suggests, as capital investment pushes the industry forward, it is met with increasingly demanding technological and managerial challenges.
Intel’s struggles with its 10nm process exemplified this challenge, but it is far from unique.
We’ve known for years that each new node brought greater challenges and tougher problems than the previous; that’s why fewer and fewer foundries bother operating on the leading edge at all. Intel might not have been the company anyone expected to slip, but the chances that somebody would have been rising every node.[45]
As semiconductor manufacturing approaches the physical limits of Moore’s Law, each new node presents unprecedented engineering challenges that can derail even the most experienced companies. And this technological risk manifests at multiple levels of the innovation stack.[46]
Lithography—the process by which a semiconductor’s intricate design is transferred from a template to actual silicon—was Intel’s undoing at the 10nm node.[47] Rather than adopt the latest technique (EUV), Intel attempted to shoehorn older technology into its new design.[48] “This decision—driven by poor management choices and a lack of technical expertise at the leadership level—led to Intel falling behind in process node advancements, missing deadlines, and losing its technological edge.”[49] TSMC and Samsung’s decision to embrace EUV despite these challenges ultimately proved correct, but Intel’s attempt to avoid these costs through advanced multi-patterning techniques was not unreasonable given the information available. Implementation of the then-bleeding-edge EUV technology also entailed significant and costly ancillary technological modifications that were not obviously cost-effective at the time.[50]
In fact, each node transition demands breakthrough innovations across dozens of interdependent technologies, requiring companies to solve new physics and engineering challenges that can derail even the most experienced firms. The shift at 22nm, for instance, entailed a fundamental change in chip architecture from a flat (2D) structure to an upright, three-dimensional design.[51] The current transition has introduced a formidable set of problems for, among other things, power delivery and metrology (the science of measurement)[52]—considerable manufacturing hurdles that explain difficulties like Samsung’s low initial yields at 3nm.[53] Looking forward, manufacturers must now deal with the subatomic complications of materials and design, where performance is limited by the fundamentals of quantum mechanics (e.g., wave-particle duality[54]), which allow electrons to tunnel through semiconductor barriers that are meant to stop them.[55]
As a result of this technological interdependence, execution risk is pervasive and unforgiving. The complexity creates multiple potential failure points where a single technical or manufacturing bottleneck can derail an entire generation of products. As scaling approaches physical limits, R&D challenges (like EUV lithography development, new transistor architectures, 3D heterogeneous integration, etc.) are formidable. There is no guarantee that a given approach will succeed on schedule—or at all.[56]
If a firm falls one cycle behind, it can suffer significant harm, leading to lost customers and diminished market share that are difficult (although not impossible) to recover. This is essentially what happened to Intel, which, by 2020, had lost the process leadership it held for decades.[57]
The severity of these challenges has forced some major players to exit the leading-edge race entirely. GlobalFoundries in 2018 decided to halt development of 7nm chips, essentially ceding the leading-edge race, because it determined the investment risk was too high relative to likely returns.[58] More recently, Intel has expressed that it may cancel even its 14A (angstrom) chips production if it can’t win a major customer.[59] That potential exit underscores a competitive reality: only those with sufficient financial and engineering muscle, and a sound commercial strategy, can play in the leading-edge arena, and even they must carefully calculate risk and ROI. Indeed, the makeup of the semiconductor manufacturing industry over time is a stark reminder of Joseph Schumpeter’s “perennial gale of creative destruction,”[60] as the industry’s incredible organizational, technological, and process advances have also led to a stampede of firms exiting the industry, fundamentally unable to keep pace with its inexorable competitive pressures (see Figure 6).
Figure 6: Semiconductor Industry Evolution (2002-2025)
Source: Yole Group[61]
C. Market Timing and Demand-Uncertainty Risk
Alongside high costs, semiconductor competition is marked by extreme uncertainty and risk. Companies must make billion-dollar bets on unproven technologies, future market demand, and execution of complex projects—any of which can fail.[62] The path of advancing chip technology is littered with expensive missteps and outright failures that illustrate how risky this business can be. For every successful node migration or breakthrough product, there are projects that ran over budget, were delayed for years, or had to be scrapped entirely (sometimes imperiling the firms involved).
The pressures of Moore’s and Rock’s Laws, in other words, create relentless problems around market timing. Firms must invest in capacity years ahead of demand, risking oversupply or obsolescence. If they guess wrong about demand (as happened in cyclical downturns such as after the Covid-19 pandemic), they end up with costly, idle fabs. If they invest too cautiously, they may face capacity constraints and lose business to rivals. In fact, in the past few years, around a dozen high-profile semiconductor fab projects in China (backed by provincial governments and investors) went bust after burning through an estimated $50–100 billion without ever producing revenue.[63] These “zombie fabs” testify to the complexity and risk: money alone could not guarantee success when technical know-how and supply chain integration were lacking.
The immense pressure to be prescient—and the enormous costs of failing to be so—also explain why periods of apparently high margins sometimes appear when a firm “wins” a node. Economically, they are best understood as “entrepreneurial rents”—the necessary rewards when huge, risky, front-loaded bets pay off—rather than durable monopoly profits. As Pleatsikas and Teece put it, “high net margins may merely be reflective of the high returns required on successful products, given the inherent uncertainty and riskiness of such investments.”[64] Those rents are transient and typically plowed back into the next round of investment.
The relationship between the leading chip manufacturing firm, TSMC, and two of the world’s most valuable firms, Apple and Nvidia, illustrates this competitive dynamic. Some critics have suggested that TSMC’s leading position in advanced manufacturing stems from exclusionary conduct,[65] or, from a structuralist perspective, that this leading position insulates it from competitive pressures.[66] But TSMC’s leadership is perhaps best explained by its ability to anticipate technological inflection points and align its capacity expansions with customers positioned to drive those shifts. The firm’s rise to the top was not preordained; it was secured by committing billions of dollars in new fabs and process technology at moments when demand was uncertain, but where the potential rewards for getting the bet right were transformative. Indeed, famously, as Intel delayed implementation of the then-uncertain EUV technology in 2014, TSMC (and Samsung) made significant investments necessary to adapt to its technological demands and embrace it.[67]
This pattern of successful risk-taking emerged early in TSMC’s relationships with its key customers. In the 2010s, TSMC made a decisive bet on Apple’s custom processors for the iPhone, anticipating that mobile computing would define the next decade.[68] More recently, it repeated this play by expanding its advanced packaging capacity for Nvidia, correctly forecasting the surge in demand for AI-powering GPUs.[69] In both cases, TSMC’s willingness to make large, irreversible capital investments well ahead of confirmed demand achieved two critical goals.
First, it secured an essential technological edge, creating manufacturing capabilities that competitors could not readily replicate. Second, it cultivated a market of reliable customers. Because industry leaders like Apple and Nvidia designed their flagship products around technology that only TSMC could provide, thanks to these investments, they rely on the foundry for their success.
This dynamic created a profitable, but precarious, mutual reliance. Neither party is in a position to dominate the other (as each is reliant upon the other). TSMC’s customers depended on its resulting unique manufacturing capabilities to realize their innovations, while TSMC’s high-risk gamble depended on its clients purchasing sufficient volumes from TSMC. At the same time, obtaining this valuable position was the product of enormous investment risk, extensive cooperation throughout the supply chain, and entrepreneurial managerial decision-making. The ability to realize large returns in such a situation is not “returns to monopoly,” but rather the returns to entrepreneurship, risk-taking, and good governance necessary to induce the up-front investment in those capabilities.
An extended passage discussing Apple’s 2010 outreach to TSMC—in an effort to find a neutral chip supplier after its previous supplier, Samsung, used its inside knowledge of Apple’s technology to copy elements of the iPhone for its own devices—exemplifies the nature of this bilateral dependence:
In 2010, Apple operations chief Jeff Williams reached out to [TSMC’s Chairman] Morris Chang… and convinced the Taiwanese group to make a major investment. “The risk was very substantial,” Williams recalled…. “If we were to bet heavily on TSMC, there would be no backup plan. You cannot double-plan the kind of volumes that we do. We want leading-edge technology, but we want it at established technology… volumes….”
…Chang agreed to take only half of Apple’s order. Even this partial commitment forced TSMC to borrow $7 billion, so it could invest $9 billion and devote 6,000 full-time employees working round the clock to bring up a new chips fab in eleven months, according to Williams. “In the end, the execution was flawless,” he said. The partial commitment forced Apple to toggle between Samsung and TSMC, which some in Cupertino saw as a plus—it meant that Apple wasn’t beholden to just one supplier for what serves as the brain within the iPhone. But [Johnny] Srouji’s [Apple semiconductor] team found it nightmarish to manage both suppliers. So Apple turned to TSMC on an exclusive basis, establishing over-the-top contract terms to protect itself. A person familiar with the contract characterized it as saying: “We need to make sure that you’re gonna go out of business—if you’re gonna put us at risk of going out of business” [emphasis added]. It was a “mutually assured destruction” type of situation, this person says, because if TSMC didn’t perform in any given year, there’d be no iPhone. So the Apple decision was made: “We are going to put all of our eggs in one basket, and then we’re gonna guard the basket” [emphasis added].[70]
This passage illustrates a critical trade-off in semiconductor sourcing strategies. While dual sourcing from multiple foundries is technically possible and can reduce supply risk, it imposes substantial costs: maintaining parallel design teams, managing different process technologies, coordinating separate validation cycles, and often accepting performance variations between suppliers. Apple initially attempted this approach, splitting orders between Samsung and TSMC, but found the operational complexity “nightmarish.”[71] Some firms accept these costs as insurance against supply disruption: AMD, for instance, has used TSMC, GlobalFoundries, and Samsung for different products.[72] For cutting-edge designs where performance is paramount, however, most customers ultimately choose single sourcing despite the risks, preferring to manage the consequences of dependency rather than accept the delays, costs, and performance compromises of dual sourcing.
Critically, this single-supplier outcome, when it occurs, is based on mutual dependence and substantial relationship-specific investments by both parties. In that case, those investments may be prohibitively costly to duplicate simultaneously across multiple manufacturers. Single-firm sourcing is an efficient choice, given the necessary investments, rather than exclusive dealing, as is sometimes alleged.[73] As Apple’s Jeff Williams has put it, “you cannot double plan for the volumes of technology that Apple requires[,] so partnerships are key.”[74]
Moreover, these arrangements do not compel customers (or manufacturers, for that matter) into permanent commitments. Although switching entails real costs—such as chip redesign, revalidation, and coordination with a new manufacturing partner—customers still have the option to move production if a foundry’s performance declines or a competitor offers superior technology or reliability. In fact, they not only retain this option, but they frequently exercise it, as shown by (among many others) Apple moving from Samsung to TSMC,[75] Xilinx switching from UMC to Samsung and TSMC,[76] and HiSilicon (Huawei) shifting from TSMC to SMIC.[77]
Overall, the semiconductor industry operates under extraordinary risk: massive upfront investments, technological uncertainty at the edge of physics, and volatile demand that can shift dramatically in the time between investment and production. The TSMC-Apple relationship illustrates one way that firms manage these risks: through mutual dependence and trust rather than restrictive contracts—a “mutually assured destruction” arrangement where both parties’ fortunes are inextricably linked.
III. The Economics of Semiconductor Specialization: From Integration to the Fabless-Foundry Revolution
The immense risks and capital requirements of the semiconductor industry are the direct result of its technological evolution. The relentless pressures of Moore’s Law (increasing transistor density) and Rock’s Law (escalating fab costs) led to the decreased reliance on traditional vertical integration. In its place, a specialized ecosystem emerged, governed by sophisticated contracts and long-term partnerships.
This transformation is not a market failure requiring regulation. On the contrary, it is a powerful example of what institutional economists have long observed: markets create novel governance structures to solve complex coordination problems. In an environment defined by high asset specificity (mutual dependence), complex or uncertain contingencies, and repeated, ongoing relationships, simple spot-market deals are inadequate, and full vertical integration is too rigid.[78] Instead, firms mitigate the risk of “hold-up” by engaging in relational contracting: “unique, interdependent relationships, wherein unknown contingencies or the intricacy of the required responses may prevent the specification of precise performance standards.”[79]
A. The Original Model: Vertical Integration and Integrated Device Manufacturers
In the early decades of the semiconductor era, chip manufacturing was dominated by IDMs such as Intel, Texas Instruments, Motorola, and IBM. These firms controlled the entire process from designing integrated circuits to fabricating wafers, packaging, and finished chips, employing the finished product themselves.[80]
This vertically integrated model proved efficient in the industry’s early stages when technological challenges and capital requirements, while substantial, were manageable within single organizations and when market demand was more predictable. Semiconductors were also fairly standardized.[81] The IDM approach offered clear advantages for managing the then-predominant risks inherent in semiconductor manufacturing. By controlling both design and manufacturing, companies could optimize their processes for their specific products, capture the full value chain, and avoid the coordination costs and hold-up risks that might arise from dealing with external partners. Thus, when Intel developed a new microprocessor design, it could simultaneously optimize its fabrication processes for that specific chip architecture, ensuring tight integration between design intent and manufacturing capability.
While this vertically integrated model proved efficient in the industry’s early stages, it required enormous capital expenditures for each firm to maintain state-of-the-art fabrication facilities. It also required each firm, regardless of its primary specialization, to develop and maintain the technological expertise and managerial acumen required to operate and integrate these manufacturing facilities.
Perhaps most critically from a competition standpoint, it prevented design innovation from emerging outside of established incumbent firms. This constraint created a classic chicken-and-egg problem for potential new entrants. As TSMC founder Morris Chang observed, many talented integrated circuit designers at companies like Texas Instruments and General Instruments wanted to start their own businesses, “but the one thing or the biggest thing that stopped them from leaving those companies was they couldn’t raise enough money to form their own company. Because at the time… it was thought that every company needed manufacturing, needed their wafer manufacturing, and the most capital-intensive part of a semiconductor company, of an [integrated circuit] company [was] the manufacturing.”[82]
B. The Seeds of Transformation: Capacity Sharing and Specialization Pressures
The seeds of competitive transformation were planted in the early 1980s when some semiconductor companies began entrusting the manufacturing of their chips to other companies, seeking to reduce costs and access excess manufacturing capacity:
The first step that led to the outsourcing of manufacturing was when companies began sharing their in-house fabs with other companies. A company with a large fab would have excess capacity at times. To keep the lines busy, they sold that capacity to other companies who needed more.[83]
This early capacity-sharing represented the first crack in the vertically integrated model and demonstrated the potential efficiency gains from specialization.
This shift was driven by both technological and economic pressures that were intensifying as Moore’s Law and Rock’s Law began their relentless march. The rising costs of staying current with each generation of process technology meant that even large IDMs occasionally found themselves with either excess capacity (during demand downturns) or insufficient capacity (during demand surges). Sharing capacity among firms allowed better utilization of expensive fabrication assets and provided a glimpse of the benefits that full specialization might offer.
Simultaneously, the semiconductor market was evolving from standardized products toward more specialized applications. New semiconductor companies began designing application-specific integrated circuits (ASICs), creating competitive pressure for manufacturing flexibility that the rigid IDM model struggled to accommodate.[84] This specialization trend intensified competitive dynamics by allowing firms to focus resources on their core competencies rather than spreading investments across the entire value chain. But the immense amount of capital needed to implement new fabs was still a major challenge for specialized and innovative chip-design startups.
C. The Foundry Model and Competitive Democratization
The turning point came in 1987 with the founding of TSMC, which pioneered the independent foundry model: a business focused exclusively on manufacturing chips for external design firms, fundamentally altering the competitive landscape of the semiconductor industry.[85] This separation of design and fabrication enabled the emergence of “fabless” companies like Qualcomm, Broadcom, Nvidia, and later, Apple, which could focus entirely on chip architecture and innovation without the capital and managerial burden of investing in and operating expensive fabrication plants.[86]
The independent foundry business model had several innovative features. Most importantly, manufacturers positioned themselves as neutral, non-competing suppliers, allowing them to serve competing fabless firms without the “conflicts of interest” inherent in vertically integrated rivals:
“[F]abless” firms were sometimes able to convince a bigger chipmaker with spare capacity to manufacture their chips. However, they always had second-class status behind the bigger chipmakers’ own production plans. Worse, they faced the constant risk that their manufacturing partners would steal their ideas. In addition, they had to navigate manufacturing processes that were slightly different at each big chipmaker. Not having to build fabs dramatically reduced startup costs, but counting on competitors to manufacture chips was always a risky business model.[87]
The foundry model’s competitive advantages extend far beyond simple cost savings. Independent foundries can aggregate demand from multiple customers. This aggregation allows foundries to spread the risk of demand swings across diverse customer bases and optimize capacity utilization, lowering the costs of capital investment.[88] And unlike IDMs, which must size their fabrication capacity to their own product demand, independent foundries can achieve economies of scale and still maintain higher utilization rates by serving multiple customers with varying demand cycles.
Perhaps most significantly, the foundry model transformed the semiconductor industry’s innovation dynamics through what economists might term the “democratization of innovation.” For customers, “[a] big advantage of the fabless model was shedding the high fixed cost of running a fab. In effect, the fixed costs of a fab were changed to variable costs.”[89] This transformation in the manufacturing process fundamentally altered the competitive landscape for semiconductor design by allowing semiconductor design firms (and, more recently, AI hyperscalers or “system companies”)[90] to specialize in their core competency—chip architecture and innovation—without the massive capital requirements and operational complexities of maintaining fabrication facilities.
“Outsourcing via fabrication plants like TSMC reduced upfront capital expenditure leading to increased entry of small firms responsible for a wide variety of niche digital consumer products.”[91] Small companies with innovative chip designs can access the same world-class manufacturing capabilities as established players, competing on the merits of their designs rather than their access to capital. This dynamic has enabled several established semiconductor companies, particularly U.S.-based firms, to enter the ranks of the world’s most valuable companies by focusing their competitive efforts on areas of comparative advantage. Nvidia became the world’s most valuable company ($4 trillion market cap) without ever owning a fab, focusing entirely on GPU architecture and AI innovation rather than manufacturing.[92]
D. The Ecosystem Response: Governance Without Integration
The transformation to the fabless-foundry model—and the more recent development of system companies such as Google, Apple, or Nvidia designing their own chips—reflects a fundamental shift in how the industry manages technological complexity and investment risk. The modern semiconductor ecosystem has evolved into a highly specialized network where each participant focuses on its core competencies while maintaining deep interdependencies with partners throughout the value chain.
Fabricating semiconductors entails a finely tuned interplay of scientific disciplines, where mastery over materials, chemistry, and microscale engineering is essential to shape matter at near-atomic precision. This complexity creates multiple dimensions of competition and specialization opportunities throughout the value chain. The semiconductor design and manufacturing process involves numerous stages and participants, each representing potential competitive bottlenecks or advantages.
The process begins with design and development, which may occur internally within companies or through external partnerships involving customers, researchers, and electronic design automation (EDA) tools and software providers. Manufacturing requires sophisticated equipment from specialized suppliers like ASML, which has achieved near-monopoly status in extreme ultraviolet (EUV) lithography equipment essential for leading-edge production.[93] The process also depends on specialized materials and concludes with assembly, testing, and packaging services, each of which has developed its own competitive dynamics and market structures. Figure 7 pictures this productive chain:
Figure 7: Semiconductor manufacturing production chain
Elaborated by authors based on Bown and Wang (2024)[94]
This complexity creates both competitive opportunities and constraints. While specialization allows firms to achieve competitive advantages in their focus areas, it also creates transaction costs and interdependencies that can affect incentives and competitive dynamics. For instance, equipment bottlenecks can limit foundries’ ability to expand capacity or adopt new technologies. Similarly, the availability of specialized materials or packaging services can influence the competitive positions of different foundries or regions.[95] Competitive dynamics in semiconductor manufacturing, therefore, cannot be understood by examining foundries in isolation. The entire ecosystem of upstream suppliers and downstream partners shapes who can compete effectively and on what terms.
The semiconductor supply chain involves highly specialized relationships characterized by substantial asset specificity—investments that are tailored to a particular partner or transaction. Chip designers and system companies, on the one hand, and manufacturers (foundries), on the other, both make relationship-specific investments. The fabless firm might co-develop custom process tweaks for its chips, share extensive intellectual property and know-how with the foundry, and, most importantly, design its products based on a foundry’s specific process technologies. The foundry, in turn, invests in manufacturing capacity upfront and builds a substantial portion of its upcoming fabrication space and capacity in anticipation of the customer’s needs, perhaps even tailoring processes or equipment to its specific products.
These relationship-specific investments have both benefits and costs. The benefits include aligned incentives, accelerated learning, and de-risked capacity expansion for foundries. Among the costs are increased switching costs (although still much lower than for a vertically integrated firm), possible foreclosure from early-node capacity, and hold-up possibilities. Notably, these switching cost and hold-up risks apply to both foundries and fabless firms.
As a result, coordination and contracting become critical, and the risk of hold-up or dependency is a concern that shapes competitive strategy. In response, much of the industry operates through nonstandard arrangements like relational contracting and strategic partnerships (and vertical integration in key spots) to mitigate these issues. As explained by Klein, Crawford & Alchian, these arrangements can be seen as an efficient response to risk allocation in information-constrained commercial environments rather than a foreclosure strategy.[96]
These bilateral dependencies fundamentally shape how competition occurs in the industry. Competition often happens in the forming and maintaining these vertical relationships rather than through simple spot-market transactions. Foundries compete intensively for major customers, sometimes accepting lower prices initially in exchange for volume commitments and the opportunity to build long-term partnerships. Customers, on the other hand, are typically large firms (e.g., Apple, Qualcomm, Nvidia, AMD), with bargaining power; they negotiate pricing and capacity allocations and weigh the risks of single sourcing against the benefits of deep collaboration with a trusted partner. The types of relationships, of course, vary depending on the parties and products involved.
The relative importance of formal contracts versus relational governance also varies with market conditions. During periods of supply-demand imbalance—like during the severe shortages from 2020 to 2023—formal contractual commitments may become more prevalent as a means for customers to guarantee excessively scarce supply. In such circumstances, the optimal allocation of risk may look different, leading to arrangements that effectively convert some of customers’ payments to an upfront capital investment (a riskier specific asset) in exchange for greater assurance that they will receive the wafers they need, when they need them. “[F]oundry customers generally do not place purchase orders far in advance to manufacture a particular type of product,” yet, according to TSMC, “some of our customers have entered into agreements with us to pay temporary receipts in order to retain specified capacity at our fabs.”[97]
TSMC disclosed that, by late 2021, it had received about $3.8 billion in customer pre-payments for future fab capacity.[98] From the customer perspective, while such long-term contractual commitments are not the industry norm, the ability to enter into these arrangements is beneficial for mitigating risk or planning aggressive sales strategies. As Nvidia notes in its 2024 Annual Report, for example: “In periods of growth, we may place non-cancellable inventory orders for certain product components in advance of our historical lead times, pay premiums, or provide deposits to secure future supply and capacity….”[99]
However, formal long-term contracts are not the only or even the most common solution to address the risk of hold-up. Instead, long-term relationships are sustained through deeply embedded relational contracting and carefully cultivated trust. TSMC, for instance, emphasizes that once it makes a commitment to a customer, it fully devotes itself to fulfilling it, projecting its reliability as a core driver of customer loyalty.[100] The company’s stated philosophy that “customers come first” reflects a deliberate strategy of building enduring partnerships underpinned by integrity and mutual dependence.[101] Through digital platforms and regular quarterly reviews, the company sustains continuous design, engineering, and logistical collaboration—allowing customers near real-time transparency into production and yield data.[102] These mechanisms foster a governance structure where implicit expectations and reputation—rather than strict legal enforcement—ensure performance and protect against opportunistic behavior.
The types of relationships, of course, vary depending on the parties and products involved. In areas with extreme asset specificity or potential hold-up issues, we sometimes see vertical integration as a solution. Intel’s integrated device model (design and manufacturing in-house) avoids contracting issues altogether for its CPUs (although it forgoes the benefits of specialization). Some fabless companies have acquired critical design and tool capabilities to reduce dependence on third parties.[103]
Similarly, foundries have moved upstream by offering design services and providing extensive, pre-designed, modular standard cell “libraries”[104] to deepen customer relationships. When asset specificity is high, parties will try to safeguard their investments, either contractually or by aligning ownership and incentives. All this shapes competition: it’s not a simple open market where any buyer can go to any seller at any time. Instead, there’s a dance of partnerships, with companies positioning themselves strategically (through technical collaboration, long-term relationships, and, of course, deal terms) to be among the first to access new process nodes.[105] Success in this environment depends on managing these complex vertical relationships effectively. Firms that excel as reliable partners—delivering on commitments and investing in mutual success—gain competitive advantages. In other cases, the challenge of asset specificity has driven the industry to develop complex contracting practices (like prepayments and capacity agreements) and, in some cases, to consolidate or integrate, which in turn affects how competition unfolds.
The competitive dynamics are further complicated by the fact that traditional categories (IDM versus foundry; competitor versus customer) have become increasingly blurred. Intel, while building its foundry business, simultaneously relies on TSMC to manufacture some of its own advanced components.[106] Samsung operates as both a major IDM producing its own processors and Galaxy smartphone chips, and as Samsung Foundry, a contract manufacturer serving external customers. Samsung’s own mobile division reportedly rejected its in-house processor for the flagship Galaxy S25 device, forcing its chip design division to lose the contract to Qualcomm.[107] These overlapping relationships create multiple vectors of competition: firms compete for foundry customers while simultaneously competing as those customers’ chip-design rivals, and may even compete with their own foundry customers’ products in end markets.
Intel’s experience underscores these dynamics. After years of prioritizing its IDM processes, Intel concluded that the industry’s shift toward disaggregated design had made specialization and a diversified customer base too valuable to forgo. It has therefore committed substantial capital to building a true foundry business—not only developing the necessary technical capabilities, but also attempting to adopt the pricing, service, and capacity-allocation norms required to be a neutral supplier.[108] Yet the timing has proved costly. Because foundry competition is relationship-intensive, Intel’s late entry runs headlong into reputational constraints, compounded by its earlier process stumbles. The result, to date, is a strategy that may be economically sound but remains commercially unproven: despite marquee announcements and heavy investment, external wafer starts remain limited relative to established rivals.[109] The U.S. government’s unprecedented involvement[110] and recent investments by Softbank and Nvidia[111] may well help, but managing relational contracting is about much more than dollars. Regardless, Intel’s pivot, even despite headwinds, provides strong evidence that specialization delivers net benefits—while also illustrating that asset specificity and relational contracting present unique competitive challenges.
IV. Dynamic Competition: “Competition for the Market” at Each New Node
The extraordinary economic forces outlined in Sections II and III—Moore’s Law, Rock’s Law, and the recurring investment requirements they create—combined with the industry’s evolution toward specialized ecosystem relationships (described in Section III), have produced a distinctive form of competition that differs fundamentally from traditional models of market rivalry. In this section, we characterize competition in the semiconductor manufacturing market in light of those forces and using the conceptual tools of economic and management literature.
A. Technology Races and the Economics of Temporary Leadership
The combination of Moore’s technological cadence and Rock’s exponential cost escalation, operating within the specialized fabless-foundry structure, creates what economists call “competition for the market” rather than “competition in the market.”[112] In traditional industries, firms compete primarily through operational efficiency, pricing, or incremental product improvements within relatively stable market structures. Semiconductor competition, by contrast, takes the form of intense, high-stakes races for technological leadership positions that reset the competitive landscape with each new generation.
Semiconductors are capital- and infrastructure-intensive and, in many segments, platform-esque. Once an instruction-set architecture (e.g., x86, ARM) or a software platform (e.g., NVIDIA’s CUDA) becomes established, it creates powerful network effects.[113] Software ecosystems, design tools, and engineering talent cluster around the leader, and switching costs can be significant. The leading firm then enjoys increasing returns from learning, scale, and scope in design and fabrication. Accordingly, market leadership is sustained less by short-run marginal-cost advantages than by accumulated compatibility, tooling, and talent network effects.
The next leader is determined at moments of technological or architectural transition: new process nodes, new chip architectures, or new computing paradigms (e.g., AI accelerators, neuromorphic chips). Firms compete to create and capture market leadership in what is, in one sense, a new market—or at minimum a reshaped market—rather than trying to undercut each other in yesterday’s market. The payoff for the first strategy likely dwarfs the payoff for the second.
Each move to a new process node—whether from 28nm to 16nm or from 5nm to 3nm—represents a fundamental reset of competitive positioning. As Evans & Schmalensee put it, firms in such industries “engage in dynamic, Schumpeterian competition for the market, through sequential winner-take-all races to produce drastic innovations, rather than through static price/output competition in the market.”[114] The primary competitive battleground is each new technological frontier. Once a company wins that race, competition within the established segment might temporarily diminish (leading to periods of high market share for the victor). Such positions are continuously under threat from the next wave of innovation, however. This dynamic explains why high concentration in a given chip segment can be consistent with robust overall competition: what matters is that firms had to fight hard to gain their position and must keep fighting via innovation to keep it. Competition is a succession of races for market leadership—from PCs to smartphones to AI chips—rather than a static tug-of-war within a settled market structure.
Semiconductor history is replete with such winner-take-all races. In the 1990s, the foundry segment (contract chip manufacturing) was an emerging market with several contenders vying to become the go-to manufacturer for fabless designers.[115] Though TSMC now holds the lion’s share of this market for foundry services (in part because of its superior execution and scale),[116] this outcome resulted from fierce competition for the market, not the absence of competition.
Similarly, each new chip niche (e.g., GPUs for graphics and AI; mobile SoCs for smartphones) has seen an initial period of rapid innovation and competition to capture market leadership, often ending with one or two firms on top. Nvidia’s early bet on GPU computing set it apart from many would-be GPU rivals, effectively allowing it to define and lead that market for years.[117] But that lead is continuously challenged by new races. Today, the current competition to lead in AI accelerators involves not just Nvidia but agile startups and powerful system companies designing custom chips.[118]
Technological innovation in chipmaking has the power to fundamentally reshape not only industry competition but even its overall structure. The nascent U.S. startup Substrate—which has already raised over $100 million on the strength of its purported success developing a particle-accelerator–driven X-ray lithography tool—exemplifies this potential.[119] If successful, Substrate’s approach could do more than just challenge ASML in advanced lithography; it could transform how chips are produced.[120] By planning to use its equipment in its own chip-manufacturing facilities instead of selling it to independent foundries, Substrate threatens to blur the traditional lines between equipment suppliers and chip manufacturers. Such a shift would dramatically alter the industry’s competitive dynamics, leaving current industry leaders (in lithography, manufacturing, and design) to catch up.
The global semiconductor manufacturing industry has seen successive changes in industrial leadership, often following a pattern of latecomers catching up and overtaking incumbents. This is described by “catch-up cycle” theory: a newcomer country or firm can leapfrog into leadership when certain windows of opportunity open, such as disruptive technological shifts, new surges in demand, or changes in policy and institutions.[121] In a catch-up cycle, yesterday’s leader may falter and a fast-following entrant seizes the moment to become the new leader, only to potentially be dethroned in the next cycle by another entrant.
Importantly, even within a single technology generation, high market share remains temporary. When a foundry wins the initial race to a new node, competitors continue improving their processes through accumulated volume and learning. Samsung’s 5nm node had this dynamic: while TSMC led early 5nm production, Samsung’s process matured to become a viable alternative, temporarily winning customers like Qualcomm for certain products.[122] This pattern has repeated at many nodes—initial winners enjoy temporary advantages that are eroded as trailing firms climb the learning curve, ensuring that market leadership must be continuously re-earned not just across technology generations, but within them.
B. The Role of Dynamic Capabilities in Sustained Competition
In semiconductor manufacturing, sustained success depends on dynamic capabilities—a firm’s ability to continuously reconfigure and upgrade its competencies in response to technological change. Strong dynamic capabilities are much more significant than existing market shares as a predictor of outcomes. Static advantages erode quickly in this fast-moving industry; what lets certain firms stay ahead is their superior capacity to learn, adapt, and innovate repeatedly.
The concept of dynamic capabilities, developed primarily by economist David Teece (one of the authors of this paper), refers to the organizational skills and processes that enable ongoing innovation and strategic change.[123] The three pillars of dynamic capabilities are sensing, seizing, and transforming.[124] In semiconductors, dynamic capabilities matter more than ordinary (efficacy-related) capabilities or market structure for several reasons:
- Rapid changes in technology: process nodes and architecture make large shifts every few years and dwarf whatever incremental efficacy can be squeezed out of the prior generation of chips.
- Ecosystems: success depends in part on the performance of ecosystem partners (foundries, EDA tools, customers) more than it does on internal efficiencies or market structure
- Massive sunk investments: once a firm commits (“seizes”), irreversibility is set in. Dynamic capabilities (when, where, and how to invest) become critical.
- But learning is not inexorably cumulative: accumulated process knowledge becomes a strategic asset only if continuously refreshed.
Figure 8 illustrates how these dynamic capabilities operate as a continuous cycle in semiconductor competition. Each new technology generation triggers another sensing, seizing, and transforming cycle. Firms that excel at rapid learning and timely reinvestment become leaders and can stay leaders if they sustain this cycle. The way particular firms engage with these activities determines how the market gets reconstructed with each technological discontinuity. Each cycle represents competition for the market, and firms unable to maintain the sense-seize-transform rhythm lose out when the next discontinuity hits.
Figure 8: The sense, seize, and transform cycle that expresses the strength of a firm’s dynamic capabilities
Real-world cases illustrate how dynamic capabilities translate into competitive edge. Samsung Electronics, once a latecomer, leveraged dynamic capabilities to become the world’s largest memory chip maker. A study of Samsung’s rise identified key management capabilities responsible for its rise: top leaders’ foresight in seizing opportunities, rapid learning through technology licensing and absorption, aggressive product and process innovation, diversification leveraging core competencies, and timely restructuring during crises.[125] These capabilities allowed Samsung to leapfrog incumbents, exploit “windows of opportunity” in the market, and sustain growth over decades. As the study concludes, Samsung’s experience “illustrates the importance of dynamic capabilities in creating competitive advantage and sustaining growth.”[126] More recently, Samsung has yielded its title to SK Hynix, which surpassed Samsung in Q2 2025 in the high-bandwidth memory chip market.[127]
TSMC’s evolution as an independent foundry provides another compelling example. Founder Morris Chang instilled a culture of relentless improvement and customer collaboration—effectively a dynamic capability in manufacturing and service.[128] TSMC continuously refined its processes, scaled production for diverse clients, and moved swiftly on each new technology node. This adaptability and “learning by doing” allowed TSMC to outpace IDMs like IBM and Intel in the foundry business.[129] As one study put it, “companies like Apple, Amazon, Nvidia and AMD and others have been able to leverage the competencies of TSMC’s ecosystem in manufacturing and challenge the position of Intel in overall chip performance.”[130] TSMC is able to take 85-90% of the assembly line tools in one generation, combined with all the institutional knowledge, to apply to the next.[131]
The distinction between ordinary and dynamic capabilities proves crucial for understanding why some firms maintain leadership across multiple technological discontinuities while others—despite superior resources and initial positions—fail to adapt.[132] The EUV lithography transition highlights this distinction. Moving from DUV to EUV was not an incremental improvement, but what Tushman and Anderson term a “competence-destroying” discontinuity[133]—requiring foundries to recognize the need to partially abandon decades of accumulated knowledge about multi-patterning, resist chemistry, and defect management and incur the cost of adopting a novel, immature technology in order to position themselves to compete in the future.
While Intel, with superior resources and process leadership, bet on extending its existing competency,[134] TSMC committed to EUV in 2014 at a time when critical challenges remained unsolved: mask defectivity exceeded acceptable limits by orders of magnitude, resist sensitivity made high-volume manufacturing impossible, and no pellicle materials could withstand EUV power levels.[135] This was a fundamental bet on an unproven technology trajectory. The reconfiguration required was substantial. As one analysis noted, EUV required “considerably more collaboration with external partners… which conflicted with [established] specialized approaches.”[136]
TSMC’s recent success exemplifies how dynamic capabilities drive competitive outcomes. The firm has shown exceptional sensing (understanding customers in part because it was close to them)[137] and seizing (it had a lower rate-of-return criterion for new fabs and began investing in next-generation tools ahead of Intel).[138] TSMC also benefited from fortuitous timing: graphics chips, which became central to TSMC’s portfolio, turned out to be better suited for data-intensive AI applications than anyone anticipated.[139] Intel, by contrast, stumbled at 10nm, allowing TSMC to surge ahead.[140] As Ben Thompson put it when discussing a wide range of stumbling blocks for Intel: “Clearly the opportunity was not seized. What is more concerning is that the question is no longer about seizing an opportunity but about survival.”[141] This leadership transition demonstrates that competition for leadership in cutting-edge semiconductors is not mainly about efficiency or market structure; it is about who redefines the technological frontier and follows through with the required massive investment in the fabs that this entails.
Beyond patents or scale, a firm’s organizational capacity to innovate repeatedly provides the most sustainable competitive advantage in semiconductors. Companies that can manage complex R&D pipelines, rapidly integrate new knowledge, and pivot when technology or markets shift will outperform those resting on past laurels. Incumbency becomes a double-edged sword: without strong dynamic capabilities, today’s leader can become tomorrow’s laggard when the next wave of innovation hits.
Importantly, these competitive attributes are difficult to quantify (and even to identify), and their outward manifestations—e.g., a reliance on novel, nonstandard industrial organization and contractual arrangements aimed at overcoming subtle market inefficiencies—can be mistaken for anticompetitive designs.[142] As we discuss below (Section V), accounting for these crucial but ephemeral aspects of semiconductor manufacturing market dynamics is essential for ensuring that policy interventions are beneficial.
Fundamentally, each new technology generation (e.g., each node shrink or architectural shift) triggers another sensing, seizing, and transforming cycle. Firms that are capable of rapid learning and timely reinvestment become leaders and may be able to remain ahead if they can continue to exercise their dynamic capabilities. But each cycle represents a new competition for the market, and firms unable to maintain the sense–seize–transform cycle lose out when the next discontinuity hits. As a result, the market is effectively reconstituted with each technological discontinuity. Looking at today’s market share as a measure of competition is akin to judging the results of a horse race by looking at the outcome of the last race. Rather, each generation of advanced semiconductors constitutes a new race. Any market dominance is provisional; one assesses competition not by looking at the winners of the last race or even the horses in the paddock, but by looking at the horses and their jockeys once they have left the starting gate.
C. Competition Through Creative Destruction
The principal battleground for foundries is technological advancement: Who can develop the most advanced manufacturing process technology and reliably produce chips with it at scale? This is often described as a technology “arms race” on node progression.[143] The competitive dynamics here have a “winner-take-most” flavor, at least for the time being. Being first to a new node and doing so with high yields (low defect rates), can allow a foundry to capture much of the high-end market for that generation.[144] At the 5nm node (circa 2020), for example, TSMC was 6–9 months ahead of Samsung and won virtually all the major mobile orders.[145] It was even further ahead of Intel (See Figure 9).
Figure 9: Process Node Launch Timelines
Source: Howard Yu (2025)[146]
Unlike a static winner-take-all market, however, these advantages largely reset with each generation, as competitors strive to catch up or leapfrog. While Intel reached 14nm before TSMC reached 16nm, TSMC was able to leapfrog to 10nm within 2 years.[147] Intel, after technological stumbles, aimed to progress five nodes in four years[148] and leapfrog from 7nm-equivalent to below 2nm within a couple of years by adopting new transistor architecture and other innovations. This ambitious attempt ran into trouble, however. Intel originally planned a 20A process,[149] but subsequently cancelled it for foundry customers, and recently pivoted from focusing on 18A for external customers, as well, due to lack of foundry-customer demand.[150] And yet, despite these difficulties, Intel recently said that it “continue[s] to make steady progress on yield and performance targets… and we remain committed to ramping [18A] technology to scale.”[151] Indeed, “[b]y starting 18A mass production [in 2025Q4], Intel became the first among foundry competitors to bring backside power delivery to market, while its Arizona fab becomes the first in the U.S. to hit 2nm-class mass production.”[152]
This leapfrogging dynamic means that the industry’s leadership is contestable.[153] Dominance must be continually re-earned, and even a firm with a large current share faces the threat that a rival’s technological breakthrough (or its own operational misstep) could trigger a customer exodus within one or two product cycles.
Looking at the semiconductor industry overall (not just semiconductor manufacturing), the churn among the industry’s top players over the past four decades has been dramatic, with firms rising and falling in the rankings as technological waves and market shifts created new opportunities for competitive advantage (See Table 2).
Table 2: Top 10 Global Semiconductor Firms by Sales Revenue (1980-2020)
Source: Bown & Wang (2024) (Shaded companies are domiciled in the U.S.)[154]
The data reveals the transient nature of semiconductor leadership. Companies that dominated in 1980—such as Texas Instruments, Motorola, and Philips—have been displaced by firms that barely existed or were much smaller players at the time. Intel’s rise to the top by 1990 reflected its success in microprocessors, while Samsung’s ascent from a regional player to a global leader illustrates how dynamic capabilities and strategic investment can enable catch-up and overtaking. TSMC’s emergence as a top-tier player by 2020 demonstrates how the then-novel foundry model’s success created entirely new paths to industry leadership. Meanwhile, the persistence of some players like Intel across multiple decades, despite fluctuations in ranking, shows that sustained success requires continuous adaptation and reinvestment in new capabilities as technological paradigms shift.
In semiconductors, companies invest heavily in CapEx and R&D and compete for future markets through technological breakthroughs, rather than only competing on prices in mature markets.[155] The TSMC–AMD partnership’s success in challenging Intel’s decades-long dominance in PC processors and cloud computing illustrates this dynamic. Intel’s long dominance was eroded when TSMC seized upon new process techniques (EUV) while AMD improved chip designs, illustrating how continuous innovation can overturn market positions.[156] This dynamic, innovation-driven competition forces firms to “run fast” just to stay in place, creating benefits for consumers in the form of rapid performance improvements.[157]
Semiconductor competition is fundamentally Schumpeterian, driven by innovation and the “perennial gales of creative destruction” rather than simple price-cutting.[158] As Petit and Teece describe Schumpeterian competition: “New technological phenomena are born of dynamic innovation-driven competition. As we have emphasized, competition is fueled not by static price-based rivalry, even though price for unit of performance may be lower even with no innovation (due to efficiency).”[159] Firms compete to leapfrog each other with drastic technological advances, such as new chip architectures or smaller process nodes, knowing that yesterday’s cutting-edge product can become obsolete tomorrow. Indeed:
When innovation and discovery are possible, potential entrants can leapfrog an incumbent by offering superior products and services. Sunk costs depreciate more rapidly—and more unpredictably— because of ceaseless change. Potential competition, in the form of Schumpeterian “creative destruction,” could be much more vigorous in spite of sunk costs.[160]
Finally, it must be noted that exit is as much a part of dynamic competition as is entry.[161] In industries marked by these sorts of technological and process innovations with “winner-take-most” characteristics, the remainder left over for less successful firms may not be enough to maintain viability. Depending on the relative rates of entry and exit, at any given time such markets may comprise only a relatively few firms—or, more likely, only a relatively few large, established firms, with a substantial fringe of newer, smaller startups. Indeed, the inexorable direction is likely toward fewer firms, as a single, successful new competitor will invariably outcompete multiple less successful incumbents.
This dynamic is hyper-focused on first-wave demand for new nodes. Meanwhile, however, competition for second and third-wave demand—as nodes mature—becomes more price-driven and accessible to a broader range of manufacturers. This multi-phase competitive dynamic ensures that even firms that miss the initial race can compete effectively as technologies mature.
But, as importantly, this means that there is little basis to infer a lack of competition from simply counting the number of firms (or the number of “large” or “cutting-edge” firms). The relative position of each generation of leaders is always contestable, confronting them with the pressures of immediate competition even with few or no existing competitors. Thus, despite a dwindling number of leading semiconductor manufacturing firms, the intensity of CapEx and R&D investment by those firms has consistently increased, along with improvements in output, quality, price, and variety.[162]
Traditional market analysis often fixates on monopoly returns: profits earned by restricting output and charging above-competitive prices.[163] But in semiconductor manufacturing, high profits more commonly derive from other forms of returns that do not stem from anticompetitive output restriction. High margins that occasionally appear in boom years mostly reflect scarcity (limited capacity or know-how) and entrepreneurial returns (temporary excess returns due to successful innovations), not monopoly power.
Returns to scarcity or “Ricardian rents” stem from owning unique productive assets or capabilities that others cannot easily replicate. In semiconductors, this could mean proprietary intellectual property, exceptional engineering talent, or access to rare inputs. These returns are akin to those earned by the owner of a uniquely fertile land (in David Ricardo’s classic example). They do not necessarily entail reduced output; the firm is simply so much more efficient or uniquely positioned that others cannot replicate it. Michael Jordan earned Ricardian rents because of his talents, not because he restricted the output of basketball. More relevant to this industry, ASML earning high margins as the sole supplier of cutting-edge EUV lithography tools reflects a Ricardian rent based on its unique technology, not a manipulative output restriction.[164]
Returns to entrepreneurship or “Schumpeterian rents” are earned by innovators due to a temporary lead before imitators catch up. These arise because technological imitation is not instantaneous; a firm that first commercializes a breakthrough chip or process can enjoy outsized profits for a period, even as it actively produces at full capacity. Such innovation returns are transient, disappearing as competitors eventually introduce similar technologies—or even before, as the incumbent dissipates those rents in the expectation that a challenger is always right around the corner.
Importantly, both types of returns are beneficial from an innovation policy perspective: they incentivize enormous investments in R&D and capital.[165] Indeed, as Pleatsikas and Teece observe, “[w]here innovative activity is high, it is unlikely that monopoly power exists. High R&D spending relative to sales is generally an indication that participants view product performance as the ultimate arbiter of competitive strength.”[166] This dynamic explains why policies designed to address traditional market power concerns may be inappropriate or counterproductive in semiconductor manufacturing.
V. Getting Semiconductor Competition Policy Right: A Cautionary Note
The semiconductor industry’s distinctive competitive dynamics—shaped by the relentless twin pressures of Moore’s Law and Rock’s Law—demand a fundamental rethinking of how competition policy should approach this critical sector. As this paper has demonstrated, the industry operates through recurring cycles of “competition for the market” rather than traditional “competition in the market,” where firms engage in high-stakes technological races that periodically reset competitive positions with each new process node.
Recent enforcement actions illustrate both appropriate and potentially misguided applications of competition policy. Whatever their substantive merits, the European Commission’s cases against Qualcomm and Broadcom, for example, appropriately targeted specific alleged exclusionary practices—such as payments conditioned on exclusive sourcing arrangements—that could foreclose rivals during critical market entry periods.[167] These interventions focused on conduct rather than market structure, recognizing that high market shares alone do not necessarily indicate anticompetitive behavior.[168]
More recently, by contrast, antitrust advocates and industrial policy proponents have raised concerns about the competitive dynamics in the foundry segment and the AI tech stack. This reflects a misreading of industry structure and dynamics. The American Economic Liberties Project, for instance, argues that “[t]he U.S. semiconductor industry used to be competitive and vibrant, but today it is too concentrated and is plagued by many of the dangers one would expect from a consolidated sector, notably shortages, weak innovation, high prices, and the pooling of risk by a monopolist.”[169] This is attributed to “[t]wo decades of patent abuse, exclusive deals, cheap money, and weak antitrust enforcement.”[170]
This critique fundamentally misunderstands the nature of competition in semiconductors, however. Its blindness to dynamic competition leads it to misattribute to market concentration what actually reflects the competitive dynamics of these markets, where the natural economics of Moore’s and Rock’s Laws interact with complex global supply chains and extreme demand volatility. The analysis presented in this paper suggests that standard indicators of market power—high market shares, long-term contracts, and customer relationship “stickiness”—are likely misleading in the semiconductor context.[171] These features often reflect the natural result of technological and economic forces rather than strategic behavior designed to exclude rivals. The semiconductor industry’s recurring pattern of competition for the market is characterized by fierce competition for technological leadership that resets with each generation, rather than a traditional winner-take-all race susceptible to permanent monopolization.
Getting the competitive assessment right is not merely an academic exercise; it could have profound policy consequences. Misguided analogies to digital platforms or traditional “natural monopolies” could tempt regulators into adopting preemptive measures ill-suited to the semiconductor manufacturing sector’s economics. Interventions that reduce the returns to successful innovation, constrain the formation of long-term customer relationships, or artificially fragment development efforts could undermine the incentives and coordination mechanisms that drive the industry’s remarkable pace of technological progress.
The industry’s sophisticated contractual relationships represent efficient responses to extraordinary coordination challenges rather than exclusionary arrangements. These governance solutions enable the massive, risky investments required for continued innovation. Proposals for ex ante regulation, mandatory access requirements, or industrial restructuring may seem appealing when framed as market-correcting mechanisms, but, failing to understand the market-correcting effects of the industry’s nonstandard industrial arrangements, they risk distorting the incentives and coordination mechanisms that drive the industry’s success.
From a competition enforcement perspective, agencies should resist the temptation to infer dominance or harm from structural indicators. Instead, if and when it arises, they should prioritize evidence of actual anticompetitive conduct and consumer harm, such as foreclosure or exclusionary exclusive dealing, and assess whether such behavior materially restricts rival access to fabrication capacity, essential technologies, or customers. Standard antitrust tools remain appropriate but must be applied with full appreciation of the industry’s economics, including the role of customer-driven innovation, massive capital expenditure requirements, and the high costs of switching or duplicating foundry capabilities.
On the policy side, governments should avoid measures that inadvertently entrench incumbents or stifle competition, as well as attempt to drum up demand-side competition. While targeted support for domestic manufacturing incentives may be justified on national security grounds, such support must be neutral in design and not favor specific firms or distort market demand. Policymakers should prioritize open access to global markets, encourage upstream R&D cooperation through public-private partnerships, and foster workforce development to address talent shortages. Export controls, while also potentially justified on national security grounds, can reduce competitive pressure from foreign manufacturers and should be designed carefully to minimize such effects.
Most importantly, governments should refrain from imposing artificial constraints—such as price controls, localization mandates, or excessive licensing restrictions—that undermine the incentives and flexibility required for this high-risk, high-reward sector to thrive. The semiconductor manufacturing industry’s competitive dynamics represent a compelling case study in Schumpeterian competition: rivalry through innovation and creative destruction rather than static price competition. Preserving these dynamics while addressing legitimate policy concerns requires a nuanced understanding of how technological forces shape market behavior and careful attention to the unintended consequences of even well-intentioned interventions.
An erroneous diagnosis of market power today could generate policy mistakes that choke innovation, deter entry, and ultimately reduce the availability and affordability of advanced computing power across the economy. The stakes are too high, and the industry too critical to global technological progress, to allow misunderstanding of competitive dynamics to drive counterproductive policy responses.
Endnotes
[1] In this paper, ‘integrated circuit,’ ‘microchip’ or ‘chip,’ and ‘semiconductor’ are used interchangeably. A chip is a set of electronic components patterned onto a silicon substrate. Strictly, ‘semiconductor’ refers to the substrate material on which circuits are constructed—usually silicon—whose conductivity is modified by adding impurities (‘doping’); in common usage it also refers to the chips themselves and the industry that makes them. See Daniel Nenni and Paul McLellan, Fabless: The Transformation of the Semiconductor Industry, loc. 54 (2013) (e-book); The Basics of Microchips, ASML (last visited Sep. 1, 2025), https://www.asml.com/en/technology/all-about-microchips/microchip-basics.
[2] Logic chips are the “brains” of electronic devices; they process information to complete a task. Memory chips store information. See The Basics of Microchips, id.
[3] In 1965, Gordon Moore, who later founded Intel, predicted that the number of transistors on computer chips would double approximately every two years, a pattern that became known as “Moore’s Law” and which has held true for half a century. This matters for another important reason: the cost of computing power has been decreasing at an even better pace—it has halved every one-and-a-half years over the last 60 years. See Max Roser, Hannah Ritchie & Edouard Mathieu, What Is Moore’s Law?, Our World in Data (Mar. 28, 2023), https://ourworldindata.org/moores-law.
[4] See Lewis Carroll, Through the Looking-Glass, and What Alice Found There 39 (1872): “Well, in our country,” said Alice, still panting a little, “you’d generally get to somewhere else—if you ran very fast for a long time, as we’ve been doing.” “A slow sort of country!” said the Queen. “Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!”
[5] Laura Peters, DTCO/STCO Create Path For Faster Yield Ramps, Semiconductor Engineering (Mar. 12, 2024), https://semiengineering.com/dtco-stco-create-path-for-faster-yield-ramps/.
[6] Samuel K. Moore, Keeping Moore’s Law Going Is Getting Complicated, IEEE Spectrum (May 24, 2023), https://spectrum.ieee.org/stco-system-technology-cooptimization.
[7] Smaller, better, faster: Imec presents chip scaling roadmap, Imec (Feb. 2, 2023), https://www.imec-int.com/en/articles/smaller-better-faster-imec-presents-chip-scaling-roadmap.
[8] Mark Liu & H.-S. Philip Wong, How We’ll Reach a 1 Trillion Transistor GPU. Advances in semiconductors are feeding the AI boom, IEEE Spectrum (Mar. 28, 2024), https://spectrum.ieee.org/trillion-transistor-gpu.
[9] See, e.g., Brian Potter, How to Build a $20 Billion Semiconductor Fab, Construction Physics (May 3, 2024), https://www.construction-physics.com/p/how-to-build-a-20-billion-semiconductor.
[10] In Rock’s formulation, doubling every four years.
[11] The term “fab” is used in the industry to refer to any semiconductor fabrication plant, whether run as part of an IDM (like Intel) or by an independent foundry (like TSMC). See Nenni and McLellan, supra note 1, at loc. 77.
[12] See Potter, supra note 9.
[13] See Anton Shilov, U.S. Semiconductor Renaissance: All the Upcoming Fabs, Tom’s Hardware (Aug. 29, 2022), https://www.tomshardware.com/news/new-us-fabs-everything-we-know (“Intel’s Fab 52 and Fab 62 will come online in 2024 and cost around $20 billion.”); America’s Chip Resurgence: Over $630 Billion in Semiconductor Supply Chain Investments, Semiconductor Industry Association (Last updated Jul. 28, 2025), https://www.semiconductors.org/chip-supply-chain-investments/.
[14] See Chris Miller, Chip War: The Fight for the World’s Most Critical Technology 217 (2022): By the mid-2000s, the layer of silicon dioxide on top of each transistor was only a couple of atoms thick, too small to keep a lid on all the electrons sitting in the silicon. To better control the movement of electrons, new materials and transistor designs were needed. Unlike the 2D design used since the 1960s, the 22nm node introduced a new 3D transistor, called a FinFET (pronounced finfet), that sets the two ends of the circuit and the channel of semiconductor material that connects them on top of a block, looking like a fin protruding from a whale’s back. The channel that connects the two ends of the circuit can therefore have an electric field applied not only from the top but also from the sides of the fin, enhancing control over the electrons and overcoming the electricity leakage that was threatening the performance of new generations of tiny transistors. These nanometer-scale 3D structures were crucial for the survival of Moore’s Law, but they were staggeringly difficult to make, requiring even more precision in deposition, etching, and lithography. This added uncertainty about whether the major chipmakers would all flawlessly execute the switch to FinFET architectures or whether one might fall behind.
[15] See Alexandra Alper, Stephen Nellis & Heekyong Yang, Exclusive: Samsung’s new Texas chip plant cost rises above $25 billion, Reuters (Mar. 15, 2023), https://www.reuters.com/technology/samsungs-new-texas-chip-plant-cost-rises-above-25-billion-sources-2023-03-15/. See also America’s Chip Resurgence, supra note 13; Press Release, TSMC Intends to Expand Its Investment in the United States to $165 Billion to Power the Future of AI, TSMC (Mar. 4, 2025), https://pr.tsmc.com/english/news/3210.
[16] Don Clark, The Tech Cold War’s ‘Most Complicated Machine’ That’s Out of China’s Reach, New York Times (Jul. 4, 2021), https://www.nytimes.com/2021/07/04/technology/tech-cold-war-chips.html (quoting Darío Gil, senior vice president at IBM).
[17] Katie Tarasov, Exclusive look at the creation of High NA, ASML’s new $400 million chipmaking colossus, CNBC (May 22, 2025), https://www.cnbc.com/2025/05/22/exclusive-look-at-high-na-asmls-new-400-million-chipmaking-colossus.html.
[18] See Taiwan Semiconductor Manufacturing Revenue 2009–2024, MacroTrends (Last visited Oct. 7, 2025), https://www.macrotrends.net/stocks/charts/TSM/taiwan-semiconductor-manufacturing/revenue.
[19] See Press Release, Biden-Harris Administration Finalize $7.86 Billion Funding Award Under US CHIPS Act, Intel (Nov. 26, 2024), https://newsroom.intel.com/corporate/intel-chips-act.
[20] Katherine Hamilton, Intel’s CHIPS Act Requirements Waived After U.S. Government Takes Stake, Morningstar (Aug. 29, 2025), https://www.morningstar.com/news/dow-jones/202508299268/intels-chips-act-requirements-waived-after-us-government-takes-stake.
[21] Semiconductor Industry Association, State of the U.S. Semiconductor Industry (2025), available at https://www.semiconductors.org/wp-content/uploads/2025/07/SIA-State-of-the-Industry-Report-2025.pdf.
[22] TSMC vs Intel in Research and Development (R&D) Spending, Stock Dividend Screener (Last updated Feb. 21, 2025), https://stockdividendscreener.com/technology/semiconductor/tsmc/research-and-development-spending-vs-intel/. It should be noted that Intel R&D expenditures also include spending related to product design, reflecting its vertically integrated structure.
[23] Semiconductor Industry Association, 2025 Factbook 19 (2025), https://www.semiconductors.org/wp-content/uploads/2025/05/2025-SIA-Factbook-FINAL-1.pdf.
[24] Id. at 12.
[25] Id. at 13.
[26] Id.
[27] Id. at 19.
[28] Id.
[29] Id. at 20.
[30] Taiwan Semiconductor Manufacturing Revenue, supra note 18.
[31] If TSMC’s $41.5 billion CapEx and R&D spend in 2022, for instance, were market cap, it would represent a firm about the size of Target or Electronic Arts, right in the middle of the S&P 500.
[32] Of course, for some firms, like Samsung and Texas Instruments, for example, it may continue to work. Other IDMs, like Intel, however, have struggled, at least in part because of the heightened managerial demands of an integrated structure. Many, like AMD, recognized the difficulties of sustaining the escalating costs of manufacturing and separated (in the case of AMD, spinning off its manufacturing division into GlobalFoundries, and eventually outsourcing the production of its most complex designs to TSMC. See Brandon Hill, AMD Commits All 7nm GPU and Zen 2 CPU Fabrication to TSMC Along with an Exec Shuffle, Hot Hardware (Aug. 27, 2018), https://hothardware.com/news/amd-7nm-gpu-zen-2-cpu-fab-tsmc.
[33] See Section IV.
[34] The most important cautionary tale—and then Cinderella story—in this regard is Intel. “Intel famously flubbed its initial 10 nanometer and 7 nanometer processes, and that gave rival AMD the jump in the server CPU market and also meant that Intel could not field GPU accelerators that could compete against Nvidia and AMD GPUs. Intel skipped 5 nanometer and 4 nanometer processes….” Timothy Prickett Morgan, Intel Puts the Process Horse Back in Front of the Foundry Cart, The Next Platform (Jul. 26, 2025), https://www.nextplatform.com/2025/07/25/intel-puts-the-process-horse-back-in-front-of-the-foundry-cart/. But now Intel’s “18A [for 18 angstrom] process is akin to a refined 2 nanometer process.” Id. And some sources suggest that Intel’s 18A has advantages over TSMC’s N2 (for 2 nanometer). See, e.g., Anton Shilov, Intel’s 18A and TSMC’s N2 process nodes compared: Intel is faster, but TSMC is denser, Tom’s Hardware (Feb. 13, 2025), https://www.tomshardware.com/tech-industry/intels-18a-and-tsmcs-n2-process-nodes-compared-intel-is-faster-but-tsmc-is-denser. Now “Intel has begun full-scale operation of its ‘Fab 52’ plant, which applies the 18A process…. Intel has opened the race for cutting-edge 2-nanometer (nm) semiconductor technology ahead of Samsung Electronics and TSMC, which had announced plans to mass-produce 2-nanometer chips within the year.” Kang Da-eun, Intel Begins Mass Production of 2-Nanometer Chips Ahead of Rivals, The Chosun Daily (last updated Oct. 10, 2025), https://www.chosun.com/english/industry-en/2025/10/10/JXRSSAD6SFCMTJCVJBEB4PP6MU/. Intel wasn’t the first to rapidly gain and lose (and regain) industry leadership, of course. TSMC—which had produced all of Apple’s A8 chips—famously fell behind in N16, leading Apple to dual source its A9 chips. See Apple to Split 14/16nm Orders Among Foundries Into 2016, EENews Europe (Sep. 17, 2015), https://www.eenewseurope.com/en/apple-to-split-14-16nm-orders-among-foundries-into-2016/. By N10, TSMC had bounced back and became the sole-source manufacturer for Apple’s A10X iPad chips. See The 10nm Process Rollout Continues to Evolve, TechInsights (last visited Oct. 1, 2025), https://www.techinsights.com/blog/10nm-process-rollout-continues-evolve.
[35] Press Release, Intel and UMC Announce New Foundry Collaboration, Intel (Jan. 25, 2024), https://newsroom.intel.com/intel-foundry/ifs-manufacturing-news-2024.
[36] UMC Reportedly Mulls Rejoining Advanced Node Race via Rumored Intel 6nm Tie-Up, Trendforce News (Jul. 2, 2025), https://www.trendforce.com/news/2025/07/02/news-umc-reportedly-mulls-rejoining-advanced-node-race-via-rumored-intel-6nm-tie-up/.
[37] See Jonathan Goldberg, How Profitable are TSMC’s Nodes: Crunching the Numbers, Techspot (Mar. 25, 2025), https://www.techspot.com/news/107278-how-profitable-tsmc-nodes-crunching-numbers.html.
[38] See TSMC to invest $100 billion over 3 years to meet chip demand, Reuters (Apr. 1, 2021), https://www.reuters.com/article/idUSKBN2BO3ZJ/.
[39] See Press Release, Micron Announces Historic Investment of up to $100 Billion to Build Megafab in Central New York, Micron (Oct. 4, 2022), https://investors.micron.com/news-releases/news-release-details/micron-announces-historic-investment-100-billion-build-megafab. See also Anton Shilov, Intel: Our Goal Is to Become Second Largest Foundry by 2030, Tom’s Hardware (Nov. 4, 2022), https://www.tomshardware.com/news/intel-our-goal-is-to-become-second-largest-foundry-by-2030.
[40] See Katie Tarasov, How Samsung and Texas Instruments made the Lone Star State the hub of U.S. chip manufacturing, CNBC (Jul. 20, 2023), https://www.cnbc.com/2023/07/20/texas-becomes-chip-hub-with-47-billion-investment-from-samsung-and-ti.html; America’s Chip Resurgence, supra note 13.
[41] See Table 1.
[42] See Ben Thompson, Tesla and Samsung, Customer Service and Intel, The U.S. Semi Supply Chain, Stratechery (Jul. 29, 2025), https://stratechery.com/2025/tesla-and-samsung-customer-service-and-intel-the-u-s-semi-supply-chain/.
[43] See Kim Jaewon & Cheng Ting-Fang, Samsung delaying completion of US chip plant due to lack of customers, Nikkei Asia (Jul. 3, 2025), https://asia.nikkei.com/business/technology/samsung-delaying-completion-of-us-chip-plant-due-to-lack-of-customers.
[44] See Section III.D.
[45] Joel Hruska, Intel Acknowledges It Was ‘Too Aggressive’ with Its 10nm Plans, Extreme Tech (Jul. 18, 2019), https://www.extremetech.com/computing/295159-intel-acknowledges-its-long-10nm-delay-caused-by-being-too-aggressive.
[46] Richard Rumelt, Intel’s Fall from Grace, Strategeion (Apr. 18, 2025), https://strategeion.substack.com/p/intels-fall-from-grace.
[47] See Paul Alcorn, Intel’s 10nm is Broken, Delayed Until 2019, Tom’s Hardware (Apr. 26, 2018), https://www.tomshardware.com/news/intel-cpu-10nm-earnings-amd%2C36967.html (“10nm is Intel’s last process based on traditional photolithography, and though Krzanich didn’t dive deep into details, he listed the lithography technique as a significant contributor to the low 10nm yields. The company will switch to EUV at 7nm. Currently, Intel’s multi-patterning process is generating too many yield-reducing defects to produce 10nm cost-effectively.”).
[48] See Bradford Morgan White, Intel: Stumbling in the Spotlight, Abort Retry Fail (Apr. 26, 2025), https://www.abortretry.fail/p/intel-stumbling-in-the-spotlight: Intel’s downward trajectory started in 2015 with the delay of 10nm which provided TSMC, Samsung, and GlobalFoundries the time needed to make progress. This delay was most likely due to high amounts multi-patterning as a result of sticking with DUV as opposed to EUV. While all manufacturers use multi-patterning, high amounts of multi-patterning increases the chance of a defect meaning yields drop until the company can rid the process of errors, and in some cases Intel was using six exposures to create single features. The lower the yield the higher the cost per wafer which can make the entire process node uneconomical. See also Rumelt, supra note 46: Because Intel prided itself on leadership in the highest power and performance chips, its technical leaders developed a strategy for succeeding at 10nm with 193nm UV lithography. The basic idea was aggressive multiple patterning and new techniques like self-aligned quadruple patterning (SAQP) and even quintuple/sextuple patterning on specific layers. New materials such as cobalt were adopted for interconnects. Intel also introduced COAG (Contact Over Active Gate), positioning the contact directly atop the transistor gate to conserve space, and utilized a design featuring a “single dummy gate.”
[49] Ralph Leftwich, Intel’s Delay in Adopting EUVL Created Today’s Struggles, LinkedIn (Apr. 6, 2025), https://www.linkedin.com/pulse/intels-delay-adopting-euvl-created-todays-struggles-ralph-leftwich-njq8c/.
[50] See Rumelt, supra note 46 (“The main challenges included mask defects, partly caused by Intel’s dependence on its proprietary design rules, software, EDA tools, and workflows. In contrast, the shift to EUV demanded considerably more collaboration with external partners (including ASML, Cadence, Synopsys, etc.), which conflicted with Intel’s specialized approach.”). See also Rick Merritt, EUV Nudges Toward 10nm, EE Times (Jun. 5, 2014), https://www.eetimes.com/euv-nudges-toward-10nm/; Usman Pirzada, Intel Confirms that EUV Lithography Will Not Be Used in 10nm Production, WCCF Tech (Sep. 8, 2014), https://wccftech.com/intel-confirms-no-euv-scanners-10nm-production/.
[51] Bradford Morgan White, Intel: Winning and Losing, Abort Retry Fail (Apr. 6, 2025), https://www.abortretry.fail/p/intel-winning-and-losing (“[H]ere again, Intel led the way to an entirely new transistor technology. Up to this point, the market had used strictly planar transistors. With Intel’s 22nm process, the world entered the era of the FinFET. In a FinFET design, the gate surrounds the channel on three sides providing a reduction in power consumption and a lowering of propagation delay (the time required for signal to travel through a transistor).”).
[52] See Gate-All-Around FET (GAA FET), Semiconductor Engineering Knowledge Center (Last visited Sep. 24, 2025), https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/gate-all-around-fet/ (“By stacking these planar channels vertically, the effective channel width is increased, resulting in increased device drive current capability with less leakage, reduced power consumption, and enhanced performance. However, the unique structure of GAA transistors makes design, metrology, inspection, and test significantly more challenging and expensive.”). See also, e.g., Brian Bailey, Impact Of GAA Transistors At 3/2nm, Semiconductor Engineering (Aug. 16, 2021), https://semiengineering.com/impact-of-gaa-transistors-at-3-2nm/; Mary A. Breton, Daniel Schmidt, Andrew Greene, Julien Frougier, & Nelson Felix, Review of Nanosheet Metrology Opportunities for Technology Readiness, 21(2) Journal of Micro/Nanopatterning, Materials, and Metrology 021206 (Apr. 2022).
[53] See Samsung’s Second-Gen 3nm GAA Process Shows 20% Yields, Missing Production Goals, TechPowerUp (Nov. 11, 2024), https://www.techpowerup.com/328680/samsungs-second-gen-3-nm-gaa-process-shows-20-yields-missing-production-goals.
[54] See Daisy Dobrijevic, The Double-Slit Experiment: Is Light a Wave or a Particle?, Space.com (Mar. 23, 2022), https://www.space.com/double-slit-experiment-light-wave-or-particle.
[55] See, e.g., Mark Veerasingam, Quantum Tunneling and the Semiconductors’ Struggle in the Miniaturization Race, Medium (Jun. 2, 2023), https://medium.com/@markveerasingam/quantum-tunneling-the-semiconductors-struggle-in-the-miniaturization-race-7ef2df8f9e48 (“Quantum tunneling occurs when a particle’s wavefunction, described by the Schrödinger equation, is not required to be zero inside a barrier, allowing it to pass through the barrier.… This means electrons can just pass through the transistor thus bypassing it’s [sic] switch-like nature.”).
[56] See Anton Shilov, Intel Will Cancel 14A and Following Nodes If It Can’t Win a Major External Customer, Tom’s Hardware (Jul. 24, 2025). https://www.tomshardware.com/tech-industry/semiconductors/intel-might-cancel-14a-process-node-development-and-the-following-nodes-if-it-cant-win-a-major-external-customer-move-would-cede-leading-edge-market-to-tsmc-and-samsung.
[57] See A Timeline of the Rise and Decline of Intel, Reuters (Last updated Sep. 18, 2025), https://www.reuters.com/technology/rise-decline-intel-2025-09-18/.
[58] See Samuel K. Moore, GlobalFoundries Halts 7-Nanometer Chip Development, IEEE Spectrum (Aug. 28, 2018), https://spectrum.ieee.org/globalfoundries-halts-7nm-chip-development.
[59] See Shilov, supra note 56.
[60] Joseph Schumpeter, Capitalism, Socialism and Democracy 84 (3rd ed., 1950) (“Competition which commands a decisive cost or quality advantage and which strikes not at the margins of the profits and the outputs of the existing firms but at their foundations and their very lives. This kind of competition is… the perennial gale of creative destruction.”). See also Section IV.
[61] See Jean-Christophe Eloy, Thibault Buisson, Pierre Cambou & Emilie Jolivet, Chip Shortages: A 5nm European Fab Is Not the Answer, Yole Group (Mar. 10, 2021), https://www.yolegroup.com/strategy-insights/chip-shortages-a-5-nm-european-fab-is-not-the-answer/.
[62] See Shilov, supra note 56.
[63] See Anton Shilov, Zombie Fabs Plague China’s Chipmaking Ambitions, Failures Burning Tens of Billions of Dollars, Tom’s Hardware (Jul. 10, 2025), https://www.tomshardware.com/tech-industry/semiconductors/zombie-fabs-plague-chinas-chipmaking-ambitions-failures-burning-tens-of-billions-of-dollars.
[64] Christopher Pleatsikas & David Teece, The Analysis of Market Power in the Context of Rapid Innovation, 19 International Journal of Industrial Organization 665, 675 (2001).
[65] See, e.g., Todd Achilles, Erik Peinert & Daniel Rangel, Reshoring and Restoring: CHIPS Implementation for a Competitive Semiconductor Industry, American Economic Liberties Project Industrial Policy Series 27–28 (Feb. 2024), https://www.economicliberties.us/wp-content/uploads/2024/02/20240117-AELP-IndPolSeries-CHIPS-Paper_v4-1.pdf. See also Press Release, Economic Liberties Calls for DOJ Investigation of Apple’s Illegal Exclusive Dealings with TSMC, American Economic Liberties Project (Apr. 16, 2024), https://www.economicliberties.us/press-release/economic-liberties-calls-for-doj-investigation-of-apples-illegal-exclusive-dealing-with-tsmc.
[66] See Achilles, et al., id., at 3.
[67] On investor calls between 2016 and 2019, TSMC leadership consistently links the company’s record-breaking CapEx directly to the “7nm technology ramp.” In these calls, they would field questions from analysts about yield learning, mask costs, and tool readiness, confirming their heavy investment in solving these ancillary challenges to bring EUV to high-volume manufacturing. See, e.g., Edited Transcript–2330.TW: Q2 2018 Taiwan Semiconductor Manufacturing Co. Ltd. Earnings Call (Thomson Reuters StreetEvents, Jul. 19, 2018) at 3, available at https://investor.tsmc.com/english/encrypt/files/encrypt_file/english/2018/Q2/TSMC%202Q18%20transcript.pdf.
[68] See infra note . The investment referred there was to implement the fabs to build the iPhone chips.
[69] See Sarah Wu & Yimou Lee, Driven by AI boom, TSMC to Invest $2.9 Billion in Advanced Chip Plant in Taiwan, Reuters (Last updated Jul. 25, 2023), https://www.reuters.com/technology/tsmc-invest-nearly-29-bln-build-advanced-chip-plant-taiwan-media-2023-07-25/.
[70] Patrick McGee, Apple in China: The Capture of the World’s Greatest Company 222 (2025).
[71] Id.
[72] See Patrick Moorhead, AMD Officially Diversifies 14nm Manufacturing with Samsung, Forbes (Jul. 25, 2016), https://www.forbes.com/sites/patrickmoorhead/2016/07/25/amd-diversifies-14nm-manufacturing-with-samsung/.
[73] See, e.g., Achilles, et al., supra note 65, at 27–28.
[74] Daniel Nenni, TSMC: Semiconductors in the next ten years!, SemiWiki (Oct. 23, 2017), https://semiwiki.com/semiconductor-manufacturers/tsmc/7097-tsmc-semiconductors-in-the-next-ten-years/ (reporting on Williams’ remarks at TSMC’s 30th Anniversary Forum event).
[75] See Kumar Priyadarshi, Why Apple Left Samsung for TSMC: The Journey of iPhone Processors, techovedas (Mar. 17, 2025), https://techovedas.com/why-apple-left-samsung-for-tsmc-the-journey-of-iphone-processors/.
[76] See Dylan McGrath, Xilinx confirms: Samsung, TSMC in, UMC out at 28-nm, EDN (Feb. 22, 2010), https://www.edn.com/xilinx-confirms-samsung-tsmc-in-umc-out-at-28-nm/.
[77] See Breaking News! Huawei places 14nm order with SMIC, EETimes (Jan. 15, 2020), https://en.eeworld.com.cn/mp/s/a79803.jspx.
[78] See, e.g., Benjamin Klein, Robert G. Crawford & Armen A. Alchian, Vertical Integration, Appropriable Rents, and the Competitive Contracting Process, 21 Journal of Law & Economics 297 (1978); Oliver E. Williamson, Transaction-Cost Economics: The Governance of Contractual Relations, 22 Journal of Law & Economics 233 (1979).
[79] Charles J. Goetz & Robert E. Scott, Principles of Relational Contracts, 67 Virginia Law Review 1089, 1092 (1981).
[80] See Christophe Lécuyer, Making Silicon Valley: Innovation and the Growth of High Tech, 1930–1970, at 266–94 (2006).
[81] See Miller, Chip War, supra note 14, at 69.
[82] The Complete History and Strategy of the TSMC, Season 9, Ep. 3, Acquired Podcast (Sep. 6, 2021), https://www.acquired.fm/episodes/tsmc.
[83] Nenni and McLellan, supra note 1, at 7.
[84] Id. at 8.
[85] Id. at 65–66.
[86] See Ben Thompson, The Intel Opportunity, Stratechery (May 2, 2013), https://stratechery.com/2013/the-intel-opportunity/: Most chip designers are fabless; they create the design, then hand it off to a foundry. AMD, Nvidia, Qualcomm, MediaTek, Apple—none of them own their own factories. This certainly makes sense: manufacturing semiconductors is perhaps the most capital-intensive industry in the world, and AMD, Qualcomm, et al have been happy to focus on higher margin design work.
[87] Miller, Chip War, supra note 14, at 67. Indeed, Samsung’s violation of Apple’s trust (by stealing Apple’s designs for its own, competing phones) eventually led to Apple replacing Samsung with TSMC as its primary chip manufacturer. See Eamon Barrett, How TSMC convinced Apple it would be a trustworthy partner, landing the Taiwan company its most significant semiconductor contract to date, Fortune (Feb. 10, 2023), https://fortune.com/2023/02/10/how-tsmc-convinced-apple-it-would-be-a-trustworthy-partner-landing-the-taiwan-company-its-most-significant-semiconductor-contract-to-date/.
[88] Jeffrey T. Macher and David C. Mowery, Vertical Specialization and Industry Structure in High Technology Industries, in Business Strategy Over the Industry Lifecycle (Advances in Strategic Management, Vol. 21) (Joel A.C. Baum & Anita M. McGahan eds., 2004) at 331–32 (“Since foundries tend to produce a wider product mix, they are less exposed to these financial risks.”).
[89] Nenni and McLellan, supra note 1, at 59.
[90] Prominent hyperscalers include AWS, Google Cloud, Azure, and Oracle. These so-called “system companies” have recently begun designing their own, home-grown, specialized chips—sometimes in partnership with traditional design firms. See, e.g., Robbie Whelan, OpenAI, Broadcom Make $10 Billion Deal for Custom AI Chips, Wall Street Journal (Sep. 5, 2025), https://www.wsj.com/tech/ai/openai-broadcom-deal-ai-chips-5c7201d2. (“‘If we’re talking about hyperscalers and gigantic AI factories, it’s very hard to get access to a high number of GPUs….’ To solve this problem, OpenAI has been working with Broadcom for over a year to develop a custom chip for use in model training.”).
[91] Jeff Thurk, Outsourcing Firm Innovation, and Industry Dynamics in the Production of Semiconductors, Notre Dame Department of Economics Working Paper (April 2024), available at https://static1.squarespace.com/static/5f62428af514a02c346d9c90/t/67852eb10eac8039c0b76e8f/1736781492338/Semiconductor.pdf.
[92] See, e.g., Lisa Eadicicco, Nvidia beats Apple and Microsoft to Become the World’s First $4 Trillion Company, CNN (Last updated Jul. 9, 2025), https://www.cnn.com/2025/07/09/investing/nvidia-is-the-first-usd4-trillion-company.
[93] See, e.g., The race is on to build the world’s most complex machine, The Economist (Mar.12, 2025), https://www.economist.com/science-and-technology/2025/03/12/the-race-is-on-to-build-the-worlds-most-complex-machine.
[94] Chad P. Bown & Dan Wang, Semiconductors and Modern Industrial Policy, 38 Journal of Economic Perspectives 81, 89 (2024).
[95] For example, in 2023–24, limited advanced-packaging (CoWoS) capacity at TSMC became the binding constraint on shipments of Nvidia’s AI GPUs. See Mark Tyson, TSMC Boosts CoWoS Production 20% to Meet Surging Demand, Tom’s Hardware (Nov. 13, 2023), https://www.tomshardware.com/news/tsmc-expands-cowos-capacity-by-20-percent.
[96] See Klein, et al., supra note 78.
[97] TSMC Form 20-F (2024 Annual Report) (filed Apr. 17, 2025) at 16, available at https://investor.tsmc.com/english/sec-filings.
[98] See Anton Shilov, TSMC Gets Billions in Prepayments for Fab Capacity, Tom’s Hardware (Nov. 17, 2021), https://www.tomshardware.com/news/tsmc-collects-huge-prepayments.
[99] NVIDIA Corp. Form 10-K (2024 Annual Report) (filed Feb. 26, 2025) at 8-9, available at https://investor.nvidia.com/financial-info/sec-filings/default.aspx.
[100] As one discussion notes of TSMC’s relationship with Apple, “establishing those high-level, executive relationships early on was integral to developing trust between the two companies. By putting its key people in the room, TSMC demonstrated its commitment to a ‘long-term relationship’ with Apple…, and assured Apple’s management that the manufacturer was taking Apple’s concerns seriously.” Barrett, supra note 87.
[101] See About TSMC: Values and Philosophy, TSMC (Last visited Oct. 1, 2025), https://www.tsmc.com/english/aboutTSMC/values.
[102] See TSMC, 2024 Sustainability Report (2024), available at https://esg.tsmc.com/file/public/e-AnInnovationPioneer_3.pdf.
[103] Apple, for example, purchased P. A. Semi (formerly Palo Alto Semiconductor) in 2008 to enable it to design custom chips for the iPod, iPhone, and other future mobile devices in-house. See Nick Wingfield, Jobs Still Hearts Intel, Wall Street Journal (Apr. 24, 2008), https://www.wsj.com/articles/BL-BB-855.
[104] In plain terms, instead of “making” chips, foundries help design them. They offer pre-made building blocks (standard-cell “libraries”) and ready-to-use reference designs, plus in-house or partner engineers who help customers assemble those blocks correctly for the foundry’s process. See e.g., Samsung Advanced Foundry Ecosystem, Samsung (Last visited Oct. 1, 2025), https://semiconductor.samsung.com/foundry/safe/.
[105] Reporting has repeatedly identified Apple (and at times Intel) as first adopters of TSMC’s leading nodes (e.g., 3nm), consistent with priority access for trusted, high-volume partners. See Apple, Intel become first to adopt TSMC’s latest chip tech—Nikkei, Reuters (Jul. 1, 2021), https://www.reuters.com/technology/apple-intel-become-first-adopt-tsmcs-latest-chip-tech-nikkei-2021-07-02/.
[106] See Paul Alcorn, Intel Details Core Ultra ‘Meteor Lake’ Architecture, Launches December 14, Tom’s Hardware (Last updated Sept. 19, 2023), https://www.tomshardware.com/news/intel-details-core-ultra-meteor-lake-architecture-launches-december-14. See also Figure 7.
[107] See Jeong-Soo Hwang, Chae-Yeon Kim & Eui-Myung Park, Samsung’s system chip, foundry business under close scrutiny for overhaul, KED Global (Mar. 6, 2025), https://www.kedglobal.com/korean-chipmakers/newsView/ked202503060008; John Mundy, Revealed: Why Samsung Galaxy phones keep ditching Qualcomm chips for Exynos, Tech Advisor (May 15, 2025), https://www.techadvisor.com/article/2772743/why-samsung-galaxy-phones-keep-ditching-qualcomm-chips-for-exynos.html.
[108] See Press Release, Intel Outlines Financial Framework for Foundry Business, Sets path to Margin Expansion, Intel (Apr. 2, 2024), https://www.intc.com/news-events/press-releases/detail/1687/intel-outlines-financial-framework-for-foundry-business.
[109] See Stephen Nellis & Max A. Cherney, Intel Discloses $7 Billion Operating Loss for Chip-making Unit, Reuters (Last updated Apr. 3, 2024), https://www.reuters.com/technology/intel-discloses-financials-foundry-business-2024-04-02.
[110] See Press Release, Intel and Trump Administration Reach Historic Agreement to Accelerate American Technology and Manufacturing Leadership, Intel (Aug. 22, 2025), https://newsroom.intel.com/corporate/intel-and-trump-administration-reach-historic-agreement.
[111] See Press Release, SoftBank Group and Intel Corporation Sign $2B Investment Agreement, Intel (Aug. 18, 2025), https://newsroom.intel.com/corporate/softbank-group-and-intel-corporation-sign-2b-investment-agreement. See also Press Release, NVIDIA and Intel to Develop AI Infrastructure and Personal Computing Products, Nvidia (Sep. 18, 2025), https://nvidianews.nvidia.com/news/nvidia-and-intel-to-develop-ai-infrastructure-and-personal-computing-products.
[112] Harold Demsetz, Why Regulate Utilities?, 11 Journal of Law & Economics 55 (1968). See also David S. Evans & Richard Schmalensee, Some Economic Aspects of Antitrust Analysis in Dynamically Competitive Industries, NBER Working Paper No. 8268 (2001), available at https://www.nber.org/system/files/working_papers/w8268/w8268.pdf.
[113] See Michael Cusumano, Nvidia at the Center of the Generative AI Ecosystem—For Now, Communications of the ACM (Jan. 8, 2024), https://cacm.acm.org/opinion/nvidia-at-the-center-of-the-generative-ai-ecosystem-for-now/ (on CUDA’s ecosystem/network effects).
[114] Evans and Schmalensee, supra note 112, at 1.
[115] See Nenni and McLellan, supra note 1.
[116] See Global Semiconductor Foundry Market Share, Counterpoint Research (Jul. 12, 2024), https://counterpointresearch.com/en/insights/global-semiconductor-foundry-market-share.
[117] See Cusumano, supra note 113 (“Nvidia early on introduced architectural innovations that made its GPUs the hardware of choice, initially for gaming and then for many other applications.”).
[118] These include (among others) Google’s Tensor processing unit and Amazon’s Trainium chips. See Kaz Sato & Cliff Young, An In-depth Look at Google’s First Tensor Processing Unit (TPU), Google Cloud Blog (May 12, 2017), https://cloud.google.com/blog/products/ai-machine-learning/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu; AWS Trainium, Amazon (Last visited Oct. 3, 2025), https://aws.amazon.com/ai/machine-learning/trainium/. All of which are further threatened by the race for quantum computing, which introduces potential disruption not only to competition in semiconductor design (and the way we use computers), but also semiconductor manufacturing.
[119] See Dylan Patel, Jeff Koch, Gerald Wong, & Andrew Wagner, How to Kill 2 Monopolies with 1 Tool, SemiAnalysis (Oct. 29, 2025), https://newsletter.semianalysis.com/p/how-to-kill-2-monopolies-with-1-tool; Heather Somerville, Peter Thiel-Backed Startup Secures $100 Million to Make Chips in U.S., Wall Street Journal (Oct. 28, 2025), https://www.wsj.com/tech/peter-thiel-backed-startup-secures-100-million-to-make-chips-in-u-s-baff93ac.
[120] See Patel, et al., id. (“Substrate isn’t stopping there. They intend to run the tools in their own fabs rather than sell to 3rd parties. The mission isn’t just XRL, it’s a new American foundry. The goal is to develop an entire end-to-end chipmaking process, buying off-the-shelf when suitable options exist, inventing when they don’t.”). It should be noted that the technology is, to say the least, unproven. Yet, as Patel, et al. note, while “[e]vidence so far is scarce, so we repeat these claims with some healthy skepticism…, external contacts and 3rd party reports are all telling us the same story: the litho tool is legit.” Id.
[121] Keun Lee & Franco Malerba, Catch-up Cycles and Changes in industrial Leadership: Widows of Opportunity and Responses of Firms and Countries in the Evolution of Sectoral Systems, 46 Research Policy 338 (2017), https://www.sciencedirect.com/science/article/abs/pii/S0048733316301408.
[122] See Stephen Nellis, Qualcomm Taps Samsung to Make New Flagship 5G Smartphone Chips, Reuters (Last updated Dec. 1, 2020), https://www.reuters.com/article/business/media-telecom/qualcomm-taps-samsung-to-make-new-flagship-5g-smartphone-chips-idUSL1N2IH042. By 2022 Qualcomm had returned to TSMC. See, e.g., Alan Friedman, Thanks to Poor Yields, Samsung Reportedly Loses Snapdragon Manufacturing Business to TSMC, Phone Arena (Feb. 22, 2022), https://www.phonearena.com/news/samsung-yield-on-snapdragon-chips-atrocious_id138616.
[123] See e.g., David J. Teece, Gary Pisano & Amy Shuen, Dynamic Capabilities and Strategic Management, 18 Strategic Management Journal 509 (1997).
[124] See David J. Teece, Explicating Dynamic Capabilities: The Nature and Microfoundations of (Sustainable) Enterprise Performance, 28 Strategic Management Journal 1319 (2007).
[125] Seung-Joo Lee, Dynamic Capabilities at Samsung Electronics: Analysis of its Growth Strategy in Semiconductors, KDI School Working Paper Series No. 11–07 (Aug. 2011), available at https://papers.ssrn.com/sol3/papers.cfm?abstract_id=1914116.
[126] Id. at 17.
[127] See Yoolim Lee, SK Hynix Surpasses Samsung as Top Memory Maker for First Time, Bloomberg (Jul. 31, 2025), https://www.bloomberg.com/news/articles/2025-07-31/sk-hynix-surpasses-samsung-as-top-memory-maker-for-first-time.
[128] See Ondrej Burkacky, Taeyoung Kim & Inji Yeom, Advanced chip packaging: How manufacturers can play to win, in McKinsey on Semiconductors (Ondrej Burkacky, et al. eds, 2024), available at https://www.mckinsey.com/~/media/mckinsey/industries/semiconductors/our%20insights/mckinsey%20on%20semiconductors%202024/mck_semiconductors_2024_webpdf.pdf.
[129] On cumulative learning as a driver of semiconductor manufacturing performance, see, for example, Douglas A. Irwin & Peter J. Klenow, Learning-by-Doing Spillovers in the Semiconductor Industry, 102 Journal of Political Economy 1200 (1994). On the retreat of integrated device manufacturers relative to the pure-play foundry model, see Abhirup Roy, IBM to Pay GlobalFoundries $1.5 Billion to Take Chip Unit, Reuters (Oct. 20, 2014), ibm-to-pay-globalfoundries-1-5-billion-to-take-chip-unit-idUSKCN0I908320141020.
[130] Morten Springborg, Leading Edge: Pushing the Boundaries and the Future of Compute, Worldwide Management White Paper (2020), at 6, available at https://cworldwide.com/media/deyfyvhg/leading-edge-pushing-the-boundaries-and-the-future-of-compute.pdf.
[131] Edited Transcript–2330.TW: Q2 2025 Taiwan Semiconductor Manufacturing Co. Ltd. Earnings Call (Refinitiv StreetEvents, Jul. 17, 2025), at 10, available at https://investor.tsmc.com/chinese/encrypt/files/encrypt_file/reports/2025-07/1f4f86c935f1de837672a6973154e64b26bdae57/TSMC%202Q25%20Transcript.pdf.
[132] The framework of ordinary versus dynamic capabilities originates with Sidney G. Winter, Understanding Dynamic Capabilities, 24 Strategic Management Journal 991 (2003) (distinguishing capabilities that enable firms to “make a living” in the short term from those enabling long-term adaptation and change).
[133] Michael L. Tushman & Philip Anderson, Technological Discontinuities and Organizational Environments, 31 Administrative Science Quarterly 439, 444 (1986).
[134] See, e.g., Bradford Morgan White, supra note 51.
[135] Peter Clarke, TSMC Orders EUV Lithography Tools for Production, Electronics360 (Nov. 25, 2014), https://electronics360.globalspec.com/article/4760/tsmc-orders-euv-lithography-tools-for-production.
[136] Rumelt, supra note 46.
[137] Ben Thompson, TSMC Earnings; A16 and TSMC’s Approach to Backside Power; Intel Earnings, Architecture, and AI, Stratechery (July 28, 2021), https://stratechery.com/2025/tsmc-earnings-a16-and-tsmcs-approach-to-backside-power-intel-earnings-architecture-and-ai/.
[138] Charlie Campbell, Inside the Taiwan Firm That Makes the World’s Tech Run, Time (Oct. 1, 2021), https://time.com/6102879/semiconductor-chip-shortage-tsmc/ (“Among his many breakthroughs, Chang pioneered the tactic of initially pricing chips at a loss, in the expectation that gaining an early market share would increase scale to the point when reduced costs would generate a profit.”).
[139] See Cusumano, supra note 113.
[140] See Alcorn, supra note 47.
[141] Ben Thompson, Intel Problems, Stratechery (Jan. 19, 2021), https://stratechery.com/2021/intel-problems/.
[142] There is a long and unfortunate history of antitrust institutions (including courts and enforcers) erroneously condemning nonstandard business practices as problematic deviations from a theoretical model of perfect competition. The urge to condemn practices not fully understood arises from an implicit (or sometimes explicit) assumption that deviations from perfect-model assumptions are more likely than not expressions of market power, rather than corrections of underlying market failures. See Geoffrey A. Manne & Joshua D. Wright, Innovation and the Limits of Antitrust, 6 Journal of Competition Law & Economics 153, 163–77 (2010).
[143] Byron Mckinney, Semiconductors and Chips: The 21st Century Arms Race, S&P Global (Sep. 1, 2022), https://www.spglobal.com/market-intelligence/en/news-insights/research/semiconductors-and-chips-the-21st-century-arms-race.
[144] It’s worth noting that the semiconductor industry’s node naming conventions have become increasingly divorced from actual physical measurements or performance metrics. A “7nm” node chip from one foundry may not be comparable in terms of a transistor’s physical dimensions to a similarly designated chip from another. “Today’s ‘7nm’ processes have no features that actually measure 7 nanometers, yet the terminology persists due to industry momentum and marketing considerations.” Jin Low, Is 7nm Just Marketing Hype? How to Actually Verify a Chip’s Manufacturing Process, Medium (Sep. 13, 2025), https://medium.com/ai-simplified-in-plain-english/is-7nm-just-marketing-hype-how-to-actually-verify-a-chips-manufacturing-process-bd9718515679.
[145] See Foundry Industry’s Robust Revenue Growth to Continue in 2021, Counterpoint (Jan. 11, 2021), https://www.counterpointresearch.com/insight/foundry-industry-revenue-growth-continue-2021.
[146] Howard Yu, Inside TSMC, the $1 Trillion Ghost foundry Behind Nvidia’s Crown, One Inch Ahead (Jul. 22, 2025), https://howardyu.substack.com/p/inside-tsmc-the-1-trillion-ghost.
[147] Id.
[148] See Press Release, Intel Launches World’s First Systems Foundry Designed for the AI Era, Intel (Feb. 21, 2024), https://newsroom.intel.com/intel-foundry/foundry-news-roadmaps-updates.
[149] See Anton Shilov, Intel Tapes Out Chips on 1.8nm and 2nm Production Nodes, Tom’s Hardware (Last updated Mar. 8, 2023), https://www.tomshardware.com/news/intel-completes-development-of-18a-20a-nodes.
[150] See Press Release, Continued Momentum for Intel 18A, Intel (Sep. 4, 2024), https://newsroom.intel.com/opinion/continued-momentum-for-intel-18a.
[151] See Comments from CEO Lip-Bu Tan and CFO Dave Zinsner, Intel CEO/CFO Earnings Call Comments (Jul. 24, 2025), available at https://download.intel.com/newsroom/2025/corporate/29r29Xn/Intel-2Q2025-Earnings-Call.pdf.
[152] See Intel Reportedly Begins 18A Production in Arizona, Panther Lake Reveal Set for Oct. 9, Tech PowerUp (Oct. 1, 2025), https://www.techpowerup.com/341531/intel-reportedly-begins-18a-production-in-arizona-panther-lake-reveal-set-for-oct-9.
[153] See generally William J. Baumol, Contestable Markets: An Uprising in the Theory of Industry Structure, 72 American Economic Review 1 (1982).
[154] Bown & Wang supra note 94, at 84. *Apple doesn’t technically sell chips to third parties but designs custom devices for internal use.
[155] See SIA 2025 Factbook, supra note 23, at 12–13.
[156] TSMC Annual Report 2020 (Mar. 12, 2021) at 11, available at https://investor.tsmc.com/static/annualReports/2020/english/pdf/e_all.pdf (“In addition, 7nm FinFET plus (N7+) has been in volume production since 2019, which was the first commercially available EUV foundry process technology in the world.”).
[157] See Carroll, supra note 4.
[158] See Schumpeter, supra note 60.
[159] Nicolas Petit & David Teece, Innovating Big Tech Firms and Competition Policy; Favoring Dynamic Over Static Competition, 30 Industrial & Corporate Change 1168, 1176 (2021).
[160] Jerry Ellig, Dynamic Competition and Public Policy: Technology, Innovation and Antitrust Issues 3 (2001).
[161] Measures of business dynamism focus on exit as well. See Baumol, supra note 153, at 14 (“Perhaps a bit newer is the emphasis on the importance of freedom of exit which is as crucial a requirement of contestability as is freedom of entry.”). See also, e.g., Ryan Decker, John Haltiwanger, Ron Jarmin, & Javier Miranda, The Role of Entrepreneurship in US Job Creation and Economic Dynamism, 28 Journal of Economic Perspectives 3 (2014).
[162] See, e.g. Figure 3, Figure 6, & Figure 7.
[163] See, e.g., Jean Tirole, The Theory of Industrial Organization (1988) at Ch. 1 (textbook treatment of monopoly power as higher price via restricted output).
[164] See The Race Is on to Build the Most Complex Machine, supra note 93. For more detail on ASML’s unique capabilities, see Marc Hijink, Focus: The ASML Way. Inside the Power Struggle Over the Most Complex Machine on Earth (2024).
[165] See Petit & Teece, supra note 159, at 14 (“Ricardian and Schumpeterian rents are beneficial as they incentivize investment in innovation. Monopoly rents, by contrast, are the rents society does not want to see.”).
[166] Pleatsikas & Teece, supra note 64, at 690.
[167] See Commission Decision of 24 January 2018 (Case AT.40220–Qualcomm (Exclusivity payments)); Commission Decision of 16 October 2019 (Case AT.40608–Broadcom).
[168] It should be noted that the Qualcomm decision was ultimately annulled by the Court, highlighting the complexity of applying traditional competition analysis to this sector. See Case T-235/18, Qualcomm, Inc. v. European Commission, ECLI:EU:T:2022:358, (Jun. 15, 2022).
[169] Achilles, et al., supra note 65 at 3.
[170] Id. at 4.
[171] See, e.g., Carl Shapiro, Antitrust in a Time of Populism, 61 International Journal of Industrial Organization 714, 730 (2018) (explaining how an increase in market concentration can reflect the forces of competition, with firms that provide better value gaining market share).
